[PATCH 05/17] MIPS: loongson32: Adapt the common code to support DT

[Keguang Zhang]

Adapt the initial functions to support devicetree.
And introduce init.c to collect these initial functions.

Signed-off-by: Keguang Zhang <keguang.zhang@xxxxxxxxx>
---
 arch/mips/loongson32/Makefile        |  2 +-
 arch/mips/loongson32/common/Makefile |  2 +-
 arch/mips/loongson32/common/prom.c   | 42 ---------------
 arch/mips/loongson32/common/time.c   | 23 --------
 arch/mips/loongson32/init.c          | 78 ++++++++++++++++++++++++++++
 5 files changed, 80 insertions(+), 67 deletions(-)
 delete mode 100644 arch/mips/loongson32/common/prom.c
 delete mode 100644 arch/mips/loongson32/common/time.c
 create mode 100644 arch/mips/loongson32/init.c

diff --git a/arch/mips/loongson32/Makefile b/arch/mips/loongson32/Makefile
index c3881af369e9..2d1b985dad71 100644
--- a/arch/mips/loongson32/Makefile
+++ b/arch/mips/loongson32/Makefile
@@ -3,7 +3,7 @@
 # Common code for all Loongson 1 based systems
 #
 
-obj-$(CONFIG_MACH_LOONGSON32) += proc.o
+obj-$(CONFIG_MACH_LOONGSON32) += init.o proc.o
 obj-$(CONFIG_MACH_LOONGSON32) += common/
 
 #
diff --git a/arch/mips/loongson32/common/Makefile b/arch/mips/loongson32/common/Makefile
index b44527b1a178..b5c2f4e0f4cc 100644
--- a/arch/mips/loongson32/common/Makefile
+++ b/arch/mips/loongson32/common/Makefile
@@ -3,4 +3,4 @@
 # Makefile for common code of loongson1 based machines.
 #
 
-obj-y	+= time.o irq.o platform.o prom.o
+obj-y	+= irq.o platform.o
diff --git a/arch/mips/loongson32/common/prom.c b/arch/mips/loongson32/common/prom.c
deleted file mode 100644
index fc580a22748e..000000000000
--- a/arch/mips/loongson32/common/prom.c
+++ /dev/null
@@ -1,42 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@xxxxxxxxx>
- *
- * Modified from arch/mips/pnx833x/common/prom.c.
- */
-
-#include <linux/io.h>
-#include <linux/init.h>
-#include <linux/memblock.h>
-#include <linux/serial_reg.h>
-#include <asm/fw/fw.h>
-
-#include <loongson1.h>
-
-unsigned long memsize;
-
-void __init prom_init(void)
-{
-	void __iomem *uart_base;
-
-	fw_init_cmdline();
-
-	memsize = fw_getenvl("memsize");
-	if(!memsize)
-		memsize = DEFAULT_MEMSIZE;
-
-	if (strstr(arcs_cmdline, "console=ttyS3"))
-		uart_base = ioremap(LS1X_UART3_BASE, 0x0f);
-	else if (strstr(arcs_cmdline, "console=ttyS2"))
-		uart_base = ioremap(LS1X_UART2_BASE, 0x0f);
-	else if (strstr(arcs_cmdline, "console=ttyS1"))
-		uart_base = ioremap(LS1X_UART1_BASE, 0x0f);
-	else
-		uart_base = ioremap(LS1X_UART0_BASE, 0x0f);
-	setup_8250_early_printk_port((unsigned long)uart_base, 0, 0);
-}
-
-void __init plat_mem_setup(void)
-{
-	memblock_add(0x0, (memsize << 20));
-}
diff --git a/arch/mips/loongson32/common/time.c b/arch/mips/loongson32/common/time.c
deleted file mode 100644
index 74ad2b17918d..000000000000
--- a/arch/mips/loongson32/common/time.c
+++ /dev/null
@@ -1,23 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright (c) 2014 Zhang, Keguang <keguang.zhang@xxxxxxxxx>
- */
-
-#include <linux/clk.h>
-#include <linux/of_clk.h>
-#include <asm/time.h>
-
-void __init plat_time_init(void)
-{
-	struct clk *clk = NULL;
-
-	/* initialize LS1X clocks */
-	of_clk_init(NULL);
-
-	/* setup mips r4k timer */
-	clk = clk_get(NULL, "cpu_clk");
-	if (IS_ERR(clk))
-		panic("unable to get cpu clock, err=%ld", PTR_ERR(clk));
-
-	mips_hpt_frequency = clk_get_rate(clk) / 2;
-}
diff --git a/arch/mips/loongson32/init.c b/arch/mips/loongson32/init.c
new file mode 100644
index 000000000000..1aada785a4a3
--- /dev/null
+++ b/arch/mips/loongson32/init.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2011-2023 Keguang Zhang <keguang.zhang@xxxxxxxxx>
+ */
+
+#include <linux/clk.h>
+#include <linux/clocksource.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/irqchip.h>
+#include <linux/of.h>
+#include <linux/of_clk.h>
+#include <asm/bootinfo.h>
+#include <asm/fw/fw.h>
+#include <asm/prom.h>
+#include <asm/time.h>
+
+#define LS1X_UART0_BASE		0x1fe40000
+#define LS1X_UART1_BASE		0x1fe44000
+#define LS1X_UART2_BASE		0x1fe48000
+#define LS1X_UART3_BASE		0x1fe4c000
+
+void __init prom_init(void)
+{
+	void __iomem *uart_base;
+
+	fw_init_cmdline();
+
+	if (strstr(arcs_cmdline, "console=ttyS3"))
+		uart_base = ioremap(LS1X_UART3_BASE, 0x0f);
+	else if (strstr(arcs_cmdline, "console=ttyS2"))
+		uart_base = ioremap(LS1X_UART2_BASE, 0x0f);
+	else if (strstr(arcs_cmdline, "console=ttyS1"))
+		uart_base = ioremap(LS1X_UART1_BASE, 0x0f);
+	else
+		uart_base = ioremap(LS1X_UART0_BASE, 0x0f);
+	setup_8250_early_printk_port((unsigned long)uart_base, 0, 0);
+}
+
+void __init plat_mem_setup(void)
+{
+	void *dtb;
+
+	dtb = get_fdt();
+	if (!dtb) {
+		pr_err("No DTB found\n");
+		return;
+	}
+
+	__dt_setup_arch(dtb);
+}
+
+void __init plat_time_init(void)
+{
+	struct clk *clk = NULL;
+	struct device_node *np;
+
+	/* Initialize LS1X clocks */
+	of_clk_init(NULL);
+
+	np = of_get_cpu_node(0, NULL);
+	if (!np) {
+		pr_err("Failed to get CPU node\n");
+		return;
+	}
+
+	/* Setup MIPS r4k timer */
+	clk = of_clk_get(np, 0);
+	if (IS_ERR(clk)) {
+		pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk));
+		return;
+	}
+
+	mips_hpt_frequency = clk_get_rate(clk) / 2;
+	clk_put(clk);
+
+	timer_probe();
+}
-- 
2.39.2