Re: [PATCH v15 2/2] clk: nuvoton: Add clock driver for ma35d1 clock controller

[Jacky Huang]

On 2023/6/19 下午 04:12, Arnd Bergmann wrote:
> On Mon, Jun 19, 2023, at 05:30, Jacky Huang wrote:
> > From: Jacky Huang <ychuang3@xxxxxxxxxxx>
> >
> > The clock controller generates clocks for the whole chip, including
> > system clocks and all peripheral clocks. This driver support ma35d1
> > clock gating, divider, and individual PLL configuration.
> >
> > There are 6 PLLs in ma35d1 SoC:
> >    - CA-PLL for the two Cortex-A35 CPU clock
> >    - SYS-PLL for system bus, which comes from the companion MCU
> >      and cannot be programmed by clock controller.
> >    - DDR-PLL for DDR
> >    - EPLL for GMAC and GFX, Display, and VDEC IPs.
> >    - VPLL for video output pixel clock
> >    - APLL for SDHC, I2S audio, and other IPs.
> > CA-PLL has only one operation mode.
> > DDR-PLL, EPLL, VPLL, and APLL are advanced PLLs which have 3
> > operation modes: integer mode, fraction mode, and spread specturm mode.
> >
> > Signed-off-by: Jacky Huang <ychuang3@xxxxxxxxxxx>
> > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
> Hi Jacky,
>
> Since I have already picked up the previous version of this patch,
> please send a diff against the version I merged please.
>
>       Arnd

Dear Arnd,

I got it. Thank you.
I will send a diff version based on the previous patch.


Best regards,
Jacky Huang