[PATCH 13/14] arm64: dts: qcom: sc7280: Fix qspi pin config

[Douglas Anderson]

Similar to sc7180 (see the patch ("arm64: dts: qcom: sc7180: Fix
trogdor qspi pin config")), we should adjust the qspi pin config for
sc7280.

I won't re-describe all the research/arguments in the sc7180 patch
here, but there are a few differences for sc7280 worth noting:

1. On herobrine the SPI flash (qspi) is wired up differently on the
   board. Rather than Cr50 and the AP being wired directly together,
   there's actually a mux that will _either_ connect the AP to the
   flash or Cr50 to the flash. This means that the internal pulls on
   Cr50 don't affect us and we should enable our own pulldowns.

2. On herobrine, EEs added an external pulldown on the MISO line. The
   argument in the schematic said that we added it (but not one on
   MOSI and CLK) because Cr50 already enabled pulldowns on MOSI and
   CLK. ...though, as per #1, those Cr50 pulldowns would only affect
   the line when the mux was swung to Cr50.

The ironic result of #1 and #2 is that the external pulldowns on
CLK/MISO/MOSI on herobrine are _exactly opposite_ of the ones on
trogdor.

3. While I still don't have the actual exact schematics for all
   variants of IDP/CRD that were produced, I have some reference
   schematics that give me a belief of how the qspi is hooked up
   there. From this, I'm fairly certain that all of the older variants
   of IDP/CRD either have a pulldown on the CLK/MOSI/MISO lines (maybe
   through a direct connect to Cr50) or have no pull (in other words,
   they don't have a pullup). I'll go ahead and enable internal
   pulldowns on all the lines since that won't hurt to double-pull if
   there's an external pulldown and it's nice to have a pulldown if
   there's nothing external. Note that this only affects _older_
   CRDs. Newer revs are considered "herobrine" (see the hoglin/zoglin
   device trees).

4. I didn't find the same strange "auto-switch-to-keeper" at suspend
   when probing on sc7280. Whatever pulls (or lack thereof) I left at
   suspend time seemed to persist into suspend.

Signed-off-by: Douglas Anderson <dianders@xxxxxxxxxxxx>
---

 .../boot/dts/qcom/sc7280-chrome-common.dtsi   | 25 +++++++++++++++++--
 .../arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 14 +++++++----
 arch/arm64/boot/dts/qcom/sc7280-idp.dtsi      | 13 ++++++----
 arch/arm64/boot/dts/qcom/sc7280.dtsi          |  9 +++++--
 4 files changed, 47 insertions(+), 14 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
index 16fb20369c01..f562e4d2b655 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
@@ -60,8 +60,9 @@ &pmk8350_pon {
  */
 &qspi {
 	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>;
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>, <&qspi_data1>;
+	pinctrl-1 = <&qspi_sleep>;
 
 	spi_flash: flash@0 {
 		compatible = "jedec,spi-nor";
@@ -85,3 +86,23 @@ wifi-firmware {
 		iommus = <&apps_smmu 0x1c02 0x1>;
 	};
 };
+
+/* PINCTRL - chrome-common pinctrl */
+
+&tlmm {
+	qspi_sleep: qspi-sleep-state {
+		pins = "gpio12", "gpio13", "gpio14", "gpio15";
+
+		/*
+		 * When we're not actively transferring we want pins as GPIOs
+		 * with output disabled so that the quad SPI IP block stops
+		 * driving them. We rely on the normal pulls configured in
+		 * the active state and don't redefine them here. Also note
+		 * that we don't need the reverse (output-enable) in the
+		 * normal mode since the "output-enable" only matters for
+		 * GPIO function.
+		 */
+		function = "gpio";
+		output-disable;
+	};
+};
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
index b6137816f2f3..e651f633341f 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
@@ -692,18 +692,22 @@ &pcie1_clkreq_n {
 };
 
 &qspi_cs0 {
-	bias-disable;
+	bias-disable;		/* External pullup */
 	drive-strength = <8>;
 };
 
 &qspi_clk {
-	bias-disable;
+	bias-pull-down;		/* No external pulls */
 	drive-strength = <8>;
 };
 
-&qspi_data01 {
-	/* High-Z when no transfers; nice to park the lines */
-	bias-pull-up;
+&qspi_data0 {
+	bias-pull-down;		/* No external pulls */
+	drive-strength = <8>;
+};
+
+&qspi_data1 {
+	bias-disable;		/* External pulldown */
 	drive-strength = <8>;
 };
 
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index 8b5293e7fd2a..6aaa77abc00b 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -636,16 +636,19 @@ &pcie1_clkreq_n {
 };
 
 &qspi_cs0 {
-	bias-disable;
+	bias-disable;		/* External pullup */
 };
 
 &qspi_clk {
-	bias-disable;
+	bias-pull-down;		/* No external pulls or external pulldown */
 };
 
-&qspi_data01 {
-	/* High-Z when no transfers; nice to park the lines */
-	bias-pull-up;
+&qspi_data0 {
+	bias-pull-down;		/* No external pulls or external pulldown */
+};
+
+&qspi_data1 {
+	bias-pull-down;		/* No external pulls or external pulldown */
 };
 
 &qup_uart5_tx {
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 71e2e51c7c7f..b98994cc8616 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -4337,8 +4337,13 @@ qspi_cs1: qspi-cs1-state {
 				function = "qspi_cs";
 			};
 
-			qspi_data01: qspi-data01-state {
-				pins = "gpio12", "gpio13";
+			qspi_data0: qspi-data0-state {
+				pins = "gpio12";
+				function = "qspi_data";
+			};
+
+			qspi_data1: qspi-data1-state {
+				pins = "gpio13";
 				function = "qspi_data";
 			};
 
-- 
2.40.0.348.gf938b09366-goog