[PATCH 2/3] perf/x86/zhaoxin: Replace open-coded model number with macros

[silviazhao]

Replace open-coded family-7 model number in arch/x86/events/zhaoxin/
core.c with the macros defined in zhaoxin-family.h.

Zhaoxin used to use non-canonical name for family 7 processors in
arch/x86/events/zhaoxin/core.c. Replace them with architecture name
to keep consistent with the macros. Following are the correspondences:
ZXD -> Wudaokou
ZXE -> Lujiazui

Signed-off-by: silviazhao <silviazhao-oc@xxxxxxxxxxx>
---
 arch/x86/events/zhaoxin/core.c | 25 +++++++++++++------------
 1 file changed, 13 insertions(+), 12 deletions(-)

diff --git a/arch/x86/events/zhaoxin/core.c b/arch/x86/events/zhaoxin/core.c
index 3e9acdaeed1e..34ccb214478c 100644
--- a/arch/x86/events/zhaoxin/core.c
+++ b/arch/x86/events/zhaoxin/core.c
@@ -14,6 +14,7 @@
 
 #include <asm/cpufeature.h>
 #include <asm/hardirq.h>
+#include <asm/zhaoxin-family.h>
 #include <asm/apic.h>
 
 #include "../perf_event.h"
@@ -36,7 +37,7 @@ static struct event_constraint zxc_event_constraints[] __read_mostly = {
 	EVENT_CONSTRAINT_END
 };
 
-static struct event_constraint zxd_event_constraints[] __read_mostly = {
+static struct event_constraint wudaokou_event_constraints[] __read_mostly = {
 
 	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* retired instructions */
 	FIXED_EVENT_CONSTRAINT(0x0082, 1), /* unhalted core clock cycles */
@@ -44,7 +45,7 @@ static struct event_constraint zxd_event_constraints[] __read_mostly = {
 	EVENT_CONSTRAINT_END
 };
 
-static __initconst const u64 zxd_hw_cache_event_ids
+static __initconst const u64 wudaokou_hw_cache_event_ids
 				[PERF_COUNT_HW_CACHE_MAX]
 				[PERF_COUNT_HW_CACHE_OP_MAX]
 				[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
@@ -148,7 +149,7 @@ static __initconst const u64 zxd_hw_cache_event_ids
 },
 };
 
-static __initconst const u64 zxe_hw_cache_event_ids
+static __initconst const u64 lujiazui_hw_cache_event_ids
 				[PERF_COUNT_HW_CACHE_MAX]
 				[PERF_COUNT_HW_CACHE_OP_MAX]
 				[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
@@ -471,7 +472,7 @@ static const struct x86_pmu zhaoxin_pmu __initconst = {
 	.max_events		= ARRAY_SIZE(zx_pmon_event_map),
 	.apic			= 1,
 	/*
-	 * For zxd/zxe, read/write operation for PMCx MSR is 48 bits.
+	 * For wudaokou/lujiazui, read/write operation for PMCx MSR is 48 bits.
 	 */
 	.max_period		= (1ULL << 47) - 1,
 	.get_event_constraints	= zhaoxin_get_event_constraints,
@@ -573,27 +574,27 @@ __init int zhaoxin_pmu_init(void)
 			X86_CONFIG(.event = 0x0f, .umask = 0x04, .inv = 0, .cmask = 0);
 
 		switch (boot_cpu_data.x86_model) {
-		case 0x1b:
-			memcpy(hw_cache_event_ids, zxd_hw_cache_event_ids,
+		case ZHAOXIN_FAM7_WUDAOKOU:
+			memcpy(hw_cache_event_ids, wudaokou_hw_cache_event_ids,
 			       sizeof(hw_cache_event_ids));
 
-			x86_pmu.event_constraints = zxd_event_constraints;
+			x86_pmu.event_constraints = wudaokou_event_constraints;
 
 			zx_pmon_event_map[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x0700;
 			zx_pmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x0709;
 
-			pr_cont("ZXD events, ");
+			pr_cont("Wudaokou events, ");
 			break;
-		case 0x3b:
-			memcpy(hw_cache_event_ids, zxe_hw_cache_event_ids,
+		case ZHAOXIN_FAM7_LUJIAZUI:
+			memcpy(hw_cache_event_ids, lujiazui_hw_cache_event_ids,
 			       sizeof(hw_cache_event_ids));
 
-			x86_pmu.event_constraints = zxd_event_constraints;
+			x86_pmu.event_constraints = wudaokou_event_constraints;
 
 			zx_pmon_event_map[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x0028;
 			zx_pmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x0029;
 
-			pr_cont("ZXE events, ");
+			pr_cont("Lujiazui events, ");
 			break;
 		default:
 			return -ENODEV;
-- 
2.17.1