Re: [PATCH v2 1/1] PCI: layerscape: Add power management support

From: Rob Herring
Date: Tue Mar 21 2023 - 15:20:22 EST

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In reply to: Frank Li: "[PATCH v2 1/1] PCI: layerscape: Add power management support"
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On Tue, Mar 21, 2023 at 11:02 AM Frank Li <Frank.Li@xxxxxxx> wrote:
>
> From: Hou Zhiqiang <Zhiqiang.Hou@xxxxxxx>
>
> Add PME_Turn_Off/PME_TO_Ack handshake sequence to PCIe devices, such as
> NVME or wifi module, and finally put the PCIe controller into D3 state
> after the L2/L3 ready state transition process completion.
>
> However, it's important to note that not all devices may be able to
> tolerate the PME_Turn_Off command. In general, fixed PCIe devices
> connected to Layerscape, such as NXP wifi devices, are able to handle
> this command.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@xxxxxxx>
> Signed-off-by: Frank Li <Frank.Li@xxxxxxx>
> ---
> Change from v1 to v2
> - fixed Bjorn Helgaas's comments
> - remove ls1043 and ls1021, which PME is not self cleaned. After check
> spec, there are PME interrupt to indicate PEM_TO_ACK command. but I
> have not these platform to debug it. I just can test ls1028 platform
> now.
>
> drivers/pci/controller/dwc/pci-layerscape.c | 219 ++++++++++++++++++-
> drivers/pci/controller/dwc/pcie-designware.h | 1 +
> 2 files changed, 211 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c
> index ed5fb492fe08..5fbc9151ff82 100644
> --- a/drivers/pci/controller/dwc/pci-layerscape.c
> +++ b/drivers/pci/controller/dwc/pci-layerscape.c
> @@ -8,9 +8,11 @@
> * Author: Minghuan Lian <Minghuan.Lian@xxxxxxxxxxxxx>
> */
>
> +#include <linux/delay.h>
> #include <linux/kernel.h>
> #include <linux/interrupt.h>
> #include <linux/init.h>
> +#include <linux/iopoll.h>
> #include <linux/of_pci.h>
> #include <linux/of_platform.h>
> #include <linux/of_address.h>
> @@ -29,10 +31,40 @@
>
> #define PCIE_IATU_NUM 6
>
> +/* PF Message Command Register */
> +#define LS_PCIE_PF_MCR 0x2c
> +#define PF_MCR_PTOMR BIT(0)
> +#define PF_MCR_EXL2S BIT(1)
> +
> +#define LS_PCIE_IS_L2(v) \
> + (((v) & PORT_LOGIC_LTSSM_STATE_MASK) == PORT_LOGIC_LTSSM_STATE_L2)
> +
> +struct ls_pcie;
> +
> +struct ls_pcie_host_pm_ops {
> + int (*pm_init)(struct ls_pcie *pcie);
> + void (*send_turn_off_message)(struct ls_pcie *pcie);
> + void (*exit_from_l2)(struct ls_pcie *pcie);
> +};

Please don't create your own private layer of ops. Especially since
there is only 1 implementation.

Almost every driver has some function to set LTSSM states. Usually
that's in .start_link(). We probably need some more general DWC op
function control this.

> +
> +struct ls_pcie_drvdata {
> + const u32 pf_off;
> + const u32 lut_off;
> + const struct ls_pcie_host_pm_ops *pm_ops;
> +};
> +
> struct ls_pcie {
> struct dw_pcie *pci;
> + const struct ls_pcie_drvdata *drvdata;
> + void __iomem *pf_base;
> + void __iomem *lut_base;
> + bool big_endian;
> + bool pm_support;
> + struct regmap *scfg;
> + int index;
> };
>
> +#define ls_pcie_pf_readl_addr(addr) ls_pcie_pf_readl(pcie, addr)
> #define to_ls_pcie(x) dev_get_drvdata((x)->dev)
>
> static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
> @@ -73,6 +105,69 @@ static void ls_pcie_fix_error_response(struct ls_pcie *pcie)
> iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR);
> }
>
> +static u32 ls_pcie_pf_readl(struct ls_pcie *pcie, u32 off)
> +{
> + if (pcie->big_endian)

You set 'big-endian' for the node, but it's only these PF registers
that are big endian?

> + return ioread32be(pcie->pf_base + off);
> +
> + return ioread32(pcie->pf_base + off);
> +}
> +
> +static void ls_pcie_pf_writel(struct ls_pcie *pcie, u32 off, u32 val)
> +{
> + if (pcie->big_endian)
> + return iowrite32be(val, pcie->pf_base + off);
> +
> + return iowrite32(val, pcie->pf_base + off);
> +}
> +
> +static void ls_pcie_send_turnoff_msg(struct ls_pcie *pcie)
> +{
> + u32 val;
> + int ret;
> +
> + val = ls_pcie_pf_readl(pcie, LS_PCIE_PF_MCR);
> + val |= PF_MCR_PTOMR;
> + ls_pcie_pf_writel(pcie, LS_PCIE_PF_MCR, val);
> +
> + ret = readx_poll_timeout(ls_pcie_pf_readl_addr, LS_PCIE_PF_MCR,
> + val, !(val & PF_MCR_PTOMR), 100, 10000);
> + if (ret)
> + dev_warn(pcie->pci->dev, "poll turn off message timeout\n");
> +}
> +
> +static void ls_pcie_exit_from_l2(struct ls_pcie *pcie)
> +{
> + u32 val;
> + int ret;
> +
> + val = ls_pcie_pf_readl(pcie, LS_PCIE_PF_MCR);
> + val |= PF_MCR_EXL2S;
> + ls_pcie_pf_writel(pcie, LS_PCIE_PF_MCR, val);
> +
> + ret = readx_poll_timeout(ls_pcie_pf_readl_addr, LS_PCIE_PF_MCR,
> + val, !(val & PF_MCR_EXL2S), 100, 10000);
> + if (ret)
> + dev_warn(pcie->pci->dev, "poll exit L2 state timeout\n");
> +}
> +
> +static int ls_pcie_pm_init(struct ls_pcie *pcie)
> +{
> + return 0;
> +}
> +
> +static void ls_pcie_set_dstate(struct ls_pcie *pcie, u32 dstate)
> +{
> + struct dw_pcie *pci = pcie->pci;
> + u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_PM);
> + u32 val;
> +
> + val = dw_pcie_readw_dbi(pci, offset + PCI_PM_CTRL);
> + val &= ~PCI_PM_CTRL_STATE_MASK;
> + val |= dstate;
> + dw_pcie_writew_dbi(pci, offset + PCI_PM_CTRL, val);
> +}
> +
> static int ls_pcie_host_init(struct dw_pcie_rp *pp)
> {
> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> @@ -86,23 +181,46 @@ static int ls_pcie_host_init(struct dw_pcie_rp *pp)
>
> ls_pcie_drop_msg_tlp(pcie);
>
> + if (pcie->drvdata->pm_ops && pcie->drvdata->pm_ops->pm_init &&
> + !pcie->drvdata->pm_ops->pm_init(pcie))
> + pcie->pm_support = true;

Just define 'pm_support' in the match data.

> +
> return 0;
> }
>
> +static struct ls_pcie_host_pm_ops ls_pcie_host_pm_ops = {
> + .pm_init = &ls_pcie_pm_init,
> + .send_turn_off_message = &ls_pcie_send_turnoff_msg,
> + .exit_from_l2 = &ls_pcie_exit_from_l2,
> +};
> +
> static const struct dw_pcie_host_ops ls_pcie_host_ops = {
> .host_init = ls_pcie_host_init,
> };
>
> +static const struct ls_pcie_drvdata ls1021a_drvdata = {
> +};
> +
> +static const struct ls_pcie_drvdata ls1043a_drvdata = {
> + .lut_off = 0x10000,
> +};
> +
> +static const struct ls_pcie_drvdata layerscape_drvdata = {
> + .lut_off = 0x80000,
> + .pf_off = 0xc0000,
> + .pm_ops = &ls_pcie_host_pm_ops,
> +};
> +
> static const struct of_device_id ls_pcie_of_match[] = {
> - { .compatible = "fsl,ls1012a-pcie", },
> - { .compatible = "fsl,ls1021a-pcie", },
> - { .compatible = "fsl,ls1028a-pcie", },
> - { .compatible = "fsl,ls1043a-pcie", },
> - { .compatible = "fsl,ls1046a-pcie", },
> - { .compatible = "fsl,ls2080a-pcie", },
> - { .compatible = "fsl,ls2085a-pcie", },
> - { .compatible = "fsl,ls2088a-pcie", },
> - { .compatible = "fsl,ls1088a-pcie", },
> + { .compatible = "fsl,ls1012a-pcie", .data = &layerscape_drvdata },
> + { .compatible = "fsl,ls1021a-pcie", .data = &ls1021a_drvdata },
> + { .compatible = "fsl,ls1028a-pcie", .data = &layerscape_drvdata },
> + { .compatible = "fsl,ls1043a-pcie", .data = &ls1043a_drvdata },
> + { .compatible = "fsl,ls1046a-pcie", .data = &layerscape_drvdata },
> + { .compatible = "fsl,ls2080a-pcie", .data = &layerscape_drvdata },
> + { .compatible = "fsl,ls2085a-pcie", .data = &layerscape_drvdata },
> + { .compatible = "fsl,ls2088a-pcie", .data = &layerscape_drvdata },
> + { .compatible = "fsl,ls1088a-pcie", .data = &layerscape_drvdata },
> { },
> };
>
> @@ -121,6 +239,8 @@ static int ls_pcie_probe(struct platform_device *pdev)
> if (!pci)
> return -ENOMEM;
>
> + pcie->drvdata = of_device_get_match_data(dev);
> +
> pci->dev = dev;
> pci->pp.ops = &ls_pcie_host_ops;
>
> @@ -131,6 +251,14 @@ static int ls_pcie_probe(struct platform_device *pdev)
> if (IS_ERR(pci->dbi_base))
> return PTR_ERR(pci->dbi_base);
>
> + pcie->big_endian = of_property_read_bool(dev->of_node, "big-endian");
> +
> + if (pcie->drvdata->lut_off)
> + pcie->lut_base = pci->dbi_base + pcie->drvdata->lut_off;
> +
> + if (pcie->drvdata->pf_off)
> + pcie->pf_base = pci->dbi_base + pcie->drvdata->pf_off;
> +
> if (!ls_pcie_is_bridge(pcie))
> return -ENODEV;
>
> @@ -139,12 +267,85 @@ static int ls_pcie_probe(struct platform_device *pdev)
> return dw_pcie_host_init(&pci->pp);
> }
>
> +static bool ls_pcie_pm_supported(struct ls_pcie *pcie)
> +{
> + if (!dw_pcie_link_up(pcie->pci)) {
> + dev_dbg(pcie->pci->dev, "Endpoint isn't present\n");
> + return false;
> + }
> +
> + return pcie->pm_support;
> +}
> +
> +#ifdef CONFIG_PM_SLEEP
> +static int ls_pcie_suspend_noirq(struct device *dev)
> +{
> + struct ls_pcie *pcie = dev_get_drvdata(dev);
> + struct dw_pcie *pci = pcie->pci;
> + u32 val;
> + int ret;
> +
> + if (!ls_pcie_pm_supported(pcie))
> + return 0;
> +
> + pcie->drvdata->pm_ops->send_turn_off_message(pcie);
> +
> + /* 10ms timeout to check L2 ready */
> + ret = readl_poll_timeout(pci->dbi_base + PCIE_PORT_DEBUG0,
> + val, LS_PCIE_IS_L2(val), 100, 10000);
> + if (ret) {
> + dev_err(dev, "PCIe link enter L2 timeout! ltssm = 0x%x\n", val);
> + return ret;
> + }
> +
> + ls_pcie_set_dstate(pcie, 0x3);
> +
> + return 0;
> +}
> +
> +static int ls_pcie_resume_noirq(struct device *dev)
> +{
> + struct ls_pcie *pcie = dev_get_drvdata(dev);
> + struct dw_pcie *pci = pcie->pci;
> + int ret;
> +
> + if (!ls_pcie_pm_supported(pcie))
> + return 0;
> +
> + ls_pcie_set_dstate(pcie, 0x0);
> +
> + pcie->drvdata->pm_ops->exit_from_l2(pcie);
> +
> + ret = ls_pcie_host_init(&pci->pp);
> + if (ret) {
> + dev_err(dev, "PCIe host init failed! ret = 0x%x\n", ret);
> + return ret;
> + }
> +
> + dw_pcie_setup_rc(&pci->pp);
> +
> + ret = dw_pcie_wait_for_link(pci);
> + if (ret) {
> + dev_err(dev, "Wait link up timeout! ret = 0x%x\n", ret);
> + return ret;
> + }
> +
> + return 0;
> +}
> +#endif /* CONFIG_PM_SLEEP */
> +
> +static const struct dev_pm_ops ls_pcie_pm_ops = {
> + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(ls_pcie_suspend_noirq,
> + ls_pcie_resume_noirq)
> +};
> +
> static struct platform_driver ls_pcie_driver = {
> .probe = ls_pcie_probe,
> .driver = {
> .name = "layerscape-pcie",
> .of_match_table = ls_pcie_of_match,
> .suppress_bind_attrs = true,
> + .pm = &ls_pcie_pm_ops,
> },
> };
> builtin_platform_driver(ls_pcie_driver);
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 79713ce075cc..7de8409e2433 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -94,6 +94,7 @@
> #define PCIE_PORT_DEBUG0 0x728
> #define PORT_LOGIC_LTSSM_STATE_MASK 0x1f
> #define PORT_LOGIC_LTSSM_STATE_L0 0x11
> +#define PORT_LOGIC_LTSSM_STATE_L2 0x15
> #define PCIE_PORT_DEBUG1 0x72C
> #define PCIE_PORT_DEBUG1_LINK_UP BIT(4)
> #define PCIE_PORT_DEBUG1_LINK_IN_TRAINING BIT(29)
> --
> 2.34.1
>

Next message: Peter Xu: "[PATCH] mm/hugetlb: Fix uffd wr-protection for CoW optimization path"
Previous message: Werner Sembach: "Re: [PATCH 2/2] Input: i8042 - add TUXEDO devices to i8042 quirk tables for partial fix"
In reply to: Frank Li: "[PATCH v2 1/1] PCI: layerscape: Add power management support"
Next in thread: Frank Li: "RE: [EXT] Re: [PATCH v2 1/1] PCI: layerscape: Add power management support"
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