Re: [PATCH 6.1,6.2,6.3 v3 1/6] counter: 104-quad-8: Fix race condition between FLAG and CNTR reads

[William Breathitt Gray]

On Sun, Mar 12, 2023 at 07:15:49PM -0400, William Breathitt Gray wrote:
> The Counter (CNTR) register is 24 bits wide, but we can have an
> effective 25-bit count value by setting bit 24 to the XOR of the Borrow
> flag and Carry flag. The flags can be read from the FLAG register, but a
> race condition exists: the Borrow flag and Carry flag are instantaneous
> and could change by the time the count value is read from the CNTR
> register.
> 
> Since the race condition could result in an incorrect 25-bit count
> value, remove support for 25-bit count values from this driver;
> hard-coded maximum count values are replaced by a LS7267_CNTR_MAX define
> for consistency and clarity.
> 
> Fixes: 28e5d3bb0325 ("iio: 104-quad-8: Add IIO support for the ACCES 104-QUAD-8")
> Cc: <stable@xxxxxxxxxxxxxxx> # 6.1.x
> Cc: <stable@xxxxxxxxxxxxxxx> # 6.2.x
> Signed-off-by: William Breathitt Gray <william.gray@xxxxxxxxxx>

Applied to counter-fixes.

William Breathitt Gray

Attachment: signature.asc
Description: PGP signature