[PATCH 01/12] mips: ralink: rt305x: define RT305X_SYSC_BASE with __iomem

[Sergio Paracuellos]

So that RT305X_SYSC_BASE can be used later in multiple functions without
needing to repeat this __iomem declaration each time

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@xxxxxxxxx>
---
 arch/mips/include/asm/mach-ralink/rt305x.h | 3 ++-
 arch/mips/ralink/rt305x.c                  | 8 +++-----
 2 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/arch/mips/include/asm/mach-ralink/rt305x.h b/arch/mips/include/asm/mach-ralink/rt305x.h
index 4d8e8c8d83ce..ef58f7bff957 100644
--- a/arch/mips/include/asm/mach-ralink/rt305x.h
+++ b/arch/mips/include/asm/mach-ralink/rt305x.h
@@ -43,7 +43,8 @@ static inline int soc_is_rt5350(void)
 	return ralink_soc == RT305X_SOC_RT5350;
 }
 
-#define RT305X_SYSC_BASE		0x10000000
+#define IOMEM(x)			((void __iomem *)(KSEG1ADDR(x)))
+#define RT305X_SYSC_BASE		IOMEM(0x10000000)
 
 #define SYSC_REG_CHIP_NAME0		0x00
 #define SYSC_REG_CHIP_NAME1		0x04
diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c
index 8b095a9dcb15..135a46517763 100644
--- a/arch/mips/ralink/rt305x.c
+++ b/arch/mips/ralink/rt305x.c
@@ -21,11 +21,10 @@
 
 static unsigned long rt5350_get_mem_size(void)
 {
-	void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
 	unsigned long ret;
 	u32 t;
 
-	t = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG);
+	t = __raw_readl(RT305X_SYSC_BASE + SYSC_REG_SYSTEM_CONFIG);
 	t = (t >> RT5350_SYSCFG0_DRAM_SIZE_SHIFT) &
 		RT5350_SYSCFG0_DRAM_SIZE_MASK;
 
@@ -142,14 +141,13 @@ void __init ralink_of_remap(void)
 
 void __init prom_soc_init(struct ralink_soc_info *soc_info)
 {
-	void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
 	unsigned char *name;
 	u32 n0;
 	u32 n1;
 	u32 id;
 
-	n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
-	n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
+	n0 = __raw_readl(RT305X_SYSC_BASE + SYSC_REG_CHIP_NAME0);
+	n1 = __raw_readl(RT305X_SYSC_BASE + SYSC_REG_CHIP_NAME1);
 
 	if (n0 == RT3052_CHIP_NAME0 && n1 == RT3052_CHIP_NAME1) {
 		unsigned long icache_sets;
-- 
2.25.1