[PATCH v2 0/2] Introduce support for AM62 DSS VP0 Divider Clock

[Aradhya Bhatia]

Introduce clock divider driver and bindings for AM62 DSS (VP0).

The OLDI transmitters in AM62 SoC, require a serial clock, which is 7
times the pixel clock required by the Video Port 0 (VP0) of the DSS.

The clock architecture is such that the relevant PLL is connected to the
DSS VP0 through a clock divider (by-7). The DSS requests the pixel clock
to the clock divider, which forwards the request to parent PLL. The PLL,
in turn, is supposed to generate a 7x pixel-clock (serial clock) to feed
the OLDI transmitters directly, and the DSS through the said divider.
This ensures that both the OLDI TXes and DSS get their required clocks.

Change Log:
v2:
  - Create separate devicetree binding and driver for the clock.
    The previous version of the series added the compatible inside the
    fixed-factor clock driver, and explicitly set the flag
    CLK_SET_RATE_PARENT to have the set clock rate request propagate to
    the parent PLL. The driver is referenced from the fixed-factor clock
    driver and modified specifically to support AM62 DSS requirements.

Links:
V1: https://lore.kernel.org/all/20221226095745.19757-1-a-bhatia1@xxxxxx/

Aradhya Bhatia (2):
  dt-bindings: clock: Add binding documentation for TI AM62 DSS Clock
  clk: keystone: Add support AM62 DSS clock divider

 .../clock/ti,am62-dss-vp0-div-clk.yaml        |  44 +++++
 drivers/clk/keystone/Kconfig                  |   9 +
 drivers/clk/keystone/Makefile                 |   1 +
 drivers/clk/keystone/clk-am62-dss.c           | 164 ++++++++++++++++++
 4 files changed, 218 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/ti,am62-dss-vp0-div-clk.yaml
 create mode 100644 drivers/clk/keystone/clk-am62-dss.c

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2.39.1