Re: [PATCH v4 char-misc-next] misc: microchip: pci1xxxx: Add OTP/EEPROM driver for the pci1xxxx switch

[Greg KH]

On Sat, Feb 11, 2023 at 05:07:43AM +0000, Tharunkumar.Pasumarthi@xxxxxxxxxxxxx wrote:
> > From: Greg KH <gregkh@xxxxxxxxxxxxxxxxxxx>
> > Sent: Thursday, February 9, 2023 2:25 PM
> > To: Tharunkumar Pasumarthi - I67821
> > <Tharunkumar.Pasumarthi@xxxxxxxxxxxxx>
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the
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> > 
> > > +     } while (data & EEPROM_CMD_EPC_BUSY_BIT);
> > 
> > That's a very busy "sit and spin" loop here, what happens if the read of the
> > bit never actually succeeds?  You just locked up the system with no way to
> > interrupt it :(
> > 
> > Please provide some sort of timeout, or way to break out of this.
> > 
> > > +
> > > +     if (data & EEPROM_CMD_EPC_TIMEOUT_BIT) {
> > > +             dev_err(&priv->pdev->dev, "EEPROM write timed out\n");
> > 
> > How can the timeout bit happen if the busy bit was still set?
> > 
> > And what can userspace do about this if it is reported?
> 
> Hi Greg,
> If EEPROM_CMD_EPC_BUSY_BIT is set for more than 30ms, it will be cleared automatically by the hardware logic and EEPROM_CMD_EPC_TIMEOUT_BIT bit will be set to indicate the timeout. User space application will inform user about timeout on EEPROM write/read when this error occurs.

Ok, if the bit being set will notify userspace of the issue, then why
also spam the kernel error log?

thanks,

greg k-h