[PATCH 2/6] dt-bindings: clock: exynos850: Add AUD and HSI main gate clocks

From: Sam Protsenko
Date: Sat Feb 11 2023 - 01:40:07 EST


Add main gate clocks for controlling AUD and HSI CMUs:
- gout_aud_cmu_aud_pclk
- gout_hsi_cmu_hsi_pclk

While at it, add missing PPMU (Performance Profiling Monitor Unit)
clocks for CMU_HSI.

Signed-off-by: Sam Protsenko <semen.protsenko@xxxxxxxxxx>
---
include/dt-bindings/clock/exynos850.h | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h
index 8bb62e43fd60..afacba338c91 100644
--- a/include/dt-bindings/clock/exynos850.h
+++ b/include/dt-bindings/clock/exynos850.h
@@ -178,7 +178,8 @@
#define IOCLK_AUDIOCDCLK5 58
#define IOCLK_AUDIOCDCLK6 59
#define TICK_USB 60
-#define AUD_NR_CLK 61
+#define CLK_GOUT_AUD_CMU_AUD_PCLK 61
+#define AUD_NR_CLK 62

/* CMU_CMGP */
#define CLK_RCO_CMGP 1
@@ -227,7 +228,10 @@
#define CLK_GOUT_MMC_CARD_ACLK 11
#define CLK_GOUT_MMC_CARD_SDCLKIN 12
#define CLK_GOUT_SYSREG_HSI_PCLK 13
-#define HSI_NR_CLK 14
+#define CLK_GOUT_HSI_PPMU_ACLK 14
+#define CLK_GOUT_HSI_PPMU_PCLK 15
+#define CLK_GOUT_HSI_CMU_HSI_PCLK 16
+#define HSI_NR_CLK 17

/* CMU_IS */
#define CLK_MOUT_IS_BUS_USER 1
--
2.39.1