Re: [PATCH v2] memory: renesas-rpc-if: Fix PHYCNT.STRTIM setting

[Lad, Prabhakar]

Hi Wolfram,

Thank you for the patch.

I am yet to test this patch on g2l (I'll test v3 as you plan to send it today).

On Wed, Jan 18, 2023 at 10:46 AM Wolfram Sang
<wsa+renesas@xxxxxxxxxxxxxxxxxxxx> wrote:
>
> From: Cong Dang <cong.dang.xn@xxxxxxxxxxx>
>
> According to the datasheets, the Strobe Timing Adjustment bit (STRTIM)
> setting is different on R-Car SoCs, i.e.
>
> R-Car H3 ES1.*  : STRTIM[2:0] is set to 0x0
> R-Car M3 ES1.*  : STRTIM[2:0] is set to 0x6
> other R-Car Gen3: STRTIM[2:0] is set to 0x7
> other R-Car Gen4: STRTIM[3:0] is set to 0xf
>
> To fix this issue, a DT match data was added to specify the setting
> for special use cases.
>
> Signed-off-by: Cong Dang <cong.dang.xn@xxxxxxxxxxx>
> Signed-off-by: Hai Pham  <hai.pham.ud@xxxxxxxxxxx>
> [wsa: rebased, restructured a little, added Gen4 support]
> Signed-off-by: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx>
> ---
<snip>
> +struct rpcif_info {
> +       enum rpcif_type type;
> +       u8 strtim;
> +};
> +
>  struct rpcif {
>         struct device *dev;
>         void __iomem *base;
> @@ -71,6 +76,7 @@ struct rpcif {
>         struct reset_control *rstc;
>         size_t size;
>         enum rpcif_type type;
I think now you can get rid of this member?

Cheers,
Prabhakar