Re: [PATCH v10 4/4] tty: serial: 8250: add DFL bus driver for Altera 16550.

[matthew . gerlach]

On Tue, 10 Jan 2023, Andy Shevchenko wrote:

> On Mon, Jan 09, 2023 at 04:30:29PM -0800, matthew.gerlach@xxxxxxxxxxxxxxx wrote:
> > From: Matthew Gerlach <matthew.gerlach@xxxxxxxxxxxxxxx>
> >
> > Add a Device Feature List (DFL) bus driver for the Altera
> > 16550 implementation of UART.
>
> ...
>
> > +static int dfh_get_u64_param_val(struct dfl_device *dfl_dev, int param_id, u64 *pval)
> > +{
> > +	size_t psize;
> > +	u64 *p;
> > +
> > +	p = dfh_find_param(dfl_dev, param_id, &psize);
> > +	if (IS_ERR(p))
> > +		return PTR_ERR(p);
>
> > +	if (psize != sizeof(u64))
> > +		return -EINVAL;
>
> If this code stays in the newer versions, make it more robust against changes,
> i.e. by using sizeof(*pval).

Yes, sizeof(*pval) would be more robust if this ode stays in the newer 
versions.

> > +	*pval = *p;
> > +
> > +	return 0;
> > +}
>
> ...
>
> > +config SERIAL_8250_DFL
> > +	tristate "DFL bus driver for Altera 16550 UART"
>
> 5
>
> > +	depends on SERIAL_8250 && FPGA_DFL
> > +	help
> > +	  This option enables support for a Device Feature List (DFL) bus
> > +	  driver for the Altera 16650 UART. One or more Altera 16650 UARTs
>
> 6
>
> Which one is correct?

Great catch! The typo has been there since v1.  I will update to 16550.

Thanks,
Matthew Gerlach

> > +	  can be instantiated in a FPGA and then be discovered during
> > +	  enumeration of the DFL bus.
> > +
> > +	  To compile this driver as a module, chose M here: the
> > +	  module will be called 8250_dfl.
>
> --
> With Best Regards,
> Andy Shevchenko