Re: [PATCH v6 1/7] perf vendor events arm64: Add common topdown L1 metrics

From: John Garry
Date: Mon Jan 09 2023 - 09:59:48 EST


On 09/01/2023 02:53, Jing Zhang wrote:
I'll factor out the pmu_core__find function in tools/perf/arch/arm64/util/pmu.c:

static const struct perf_pmu *pmu_core__find(void)

maybe name as pmu_core__find_same() or similar to indicate that we're only dealing with homogeneous cores

{
struct perf_pmu *pmu = NULL;

no need to init to NULL


while ((pmu = perf_pmu__scan(pmu))) {

1x superfluous level of ()

if (!is_pmu_core(pmu->name))
continue;

/*
* The cpumap should cover all CPUs. Otherwise, some CPUs may
* not support some events or have different event IDs.
*/
if (pmu->cpus->nr != cpu__max_cpu().cpu)
return NULL;
return pmu;
}

return NULL;
}


...


+}
diff --git a/tools/perf/util/pmu.h b/tools/perf/util/pmu.h
index 69ca000..a2f7df8 100644
--- a/tools/perf/util/pmu.h
+++ b/tools/perf/util/pmu.h
@@ -259,4 +259,5 @@ int perf_pmu__cpus_match(struct perf_pmu *pmu, struct perf_cpu_map *cpus,
    char *pmu_find_real_name(const char *name);
  char *pmu_find_alias_name(const char *name);
+int perf_pmu__get_slots(void);
I think that this name is a bit too vague. Maybe perf_pmu__cpu_cycles_per_slot() could be better.

Does cpu_cycles_per_slot mean "cpu cycles per slot"? In the documemt, Slots mean operation width.
If slots are 5, the largest value by which the STALL_SLOT PMU event may increment in one cycle is 5.
So, maybe perf_pmu__cpu_slots_per_cycle() could be more accurate?

ok, yes, fine.

Thanks,
John