Re: [PATCH v5 6/7] KVM: arm64: Mask FEAT_CCIDX

[Akihiko Odaki]

On 2023/01/06 7:22, Oliver Upton wrote:
> On Fri, Dec 30, 2022 at 06:54:51PM +0900, Akihiko Odaki wrote:
> > The CCSIDR access handler masks the associativity bits according to the
> > bit layout for processors without FEAT_CCIDX. KVM also assumes CCSIDR is
> > 32-bit where it will be 64-bit if FEAT_CCIDX is enabled. Mask FEAT_CCIDX
> > so that these assumptions hold.
> >
> > Suggested-by: Marc Zyngier <maz@xxxxxxxxxx>
> > Signed-off-by: Akihiko Odaki <akihiko.odaki@xxxxxxxxxx>
>
> FYI, I'm an idiot and replied to v4 of this patch... Forwarding comments
> below:
>
> > ---
> >   arch/arm64/kvm/sys_regs.c | 11 +++++++++++
> >   1 file changed, 11 insertions(+)
> >
> > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> > index f4a7c5abcbca..aeabf1f3370b 100644
> > --- a/arch/arm64/kvm/sys_regs.c
> > +++ b/arch/arm64/kvm/sys_regs.c
> > @@ -1124,6 +1124,12 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, struct sys_reg_desc const *r
> >   						      ID_DFR0_PERFMON_SHIFT,
> >   						      kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_4 : 0);
> >   		break;
> > +	case SYS_ID_AA64MMFR2_EL1:
> > +		val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK;
> > +		break;
> > +	case SYS_ID_MMFR4_EL1:
> > +		val &= ~ARM64_FEATURE_MASK(ID_MMFR4_CCIDX);
> > +		break;
>
> Not that it is necessarily worth addressing, but I wanted to point
> something out.
>
> This change breaks migration from older kernels on implementations w/
> FEAT_CCIDX. There is most likely exactly 0 of those in the wild, but
> we need to be careful changing user-visible stuff like this.
>
> --
> Thanks,
> Oliver

I also don't think whether FEAT_CCIDX is visible matters for any guest 
because the line size a guest would care is held in the same bits 
whether FEAT_CCIDX is implemented. But if it concerns you I can write a 
bit more code so that it won't mask CCIDX bit if it's set from the 
userspace.

Regards,
Akihiko Odaki