Re: [PATCH 1/2] phy: ti: j721e-wiz: Manage TypeC lane swap if typec-gpio-dir not specified

[Sinthu Raja M]

Hi Roger,

On Wed, Dec 14, 2022 at 3:12 PM Roger Quadros <rogerq@xxxxxxxxxx> wrote:
>
> Hi,
>
> Some more comments below.
>
> On 13/12/2022 14:48, Sinthu Raja wrote:
> > It's possible that the Type-C plug orientation on the DIR line will be
> > implemented through hardware design. In that situation, there won't be
> > an external GPIO line available, but the driver still needs to address
> > this since the DT won't use the typec-gpio-dir property.
> >
> > Add code to handle LN10 Type-C swap if typec-gpio-dir property is not
> > specified in DT.
> >
> > Remove typec-gpio-dir check to use minimum debounce from Type-C spec if
> > it is not provided in DT
> >
> > Signed-off-by: Sinthu Raja <sinthu.raja@xxxxxx>
> > ---
> >  drivers/phy/ti/phy-j721e-wiz.c | 65 +++++++++++++++++++++-------------
> >  1 file changed, 40 insertions(+), 25 deletions(-)
> >
> > diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
> > index 141b51af4427..b17eec632d49 100644
> > --- a/drivers/phy/ti/phy-j721e-wiz.c
> > +++ b/drivers/phy/ti/phy-j721e-wiz.c
> > @@ -375,6 +375,7 @@ struct wiz {
> >       struct gpio_desc        *gpio_typec_dir;
> >       int                     typec_dir_delay;
> >       u32 lane_phy_type[WIZ_MAX_LANES];
> > +     u32 lane_phy_reg[WIZ_MAX_LANES];
>
> This name looks misleading. I'll discuss about it where you are setting it.
Will change the name to master_lane_num[];
>
> >       struct clk              *input_clks[WIZ_MAX_INPUT_CLOCKS];
> >       struct clk              *output_clks[WIZ_MAX_OUTPUT_CLOCKS];
> >       struct clk_onecell_data clk_data;
> > @@ -1231,14 +1232,28 @@ static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev,
> >       int ret;
> >
> >       /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */
> > -     if (id == 0 && wiz->gpio_typec_dir) {
> > -             if (wiz->typec_dir_delay)
> > -                     msleep_interruptible(wiz->typec_dir_delay);
> > -
> > -             if (gpiod_get_value_cansleep(wiz->gpio_typec_dir))
> > -                     regmap_field_write(wiz->typec_ln10_swap, 1);
> > -             else
> > -                     regmap_field_write(wiz->typec_ln10_swap, 0);
> > +     if (id == 0 && wiz->typec_dir_delay) {
> > +             msleep_interruptible(wiz->typec_dir_delay);
> > +
> > +             if (wiz->gpio_typec_dir) {
> > +                     if (gpiod_get_value_cansleep(wiz->gpio_typec_dir))
> > +                             regmap_field_write(wiz->typec_ln10_swap, 1);
> > +                     else
> > +                             regmap_field_write(wiz->typec_ln10_swap, 0);
> > +             } else {
> > +                     /* if no typec-dir gpio was specified, and USB lines
> > +                      * are connected to Lane 0 then set LN10 SWAP bit to 1.
> > +                      */
>
> Why should lanes 1 and 0 be swapped if USB is connected to lane 0?
My Bad! I should have been more precise in mentioning the USB3 Type C.
Lanes 0 and 2 are reserved for USB3 for type-C connector lane swap.
>
> > +                     u32 num_lanes = wiz->num_lanes;
> > +                     int i;
> > +
> > +                     for (i = 0; i < num_lanes; i++) {
> > +                             if ((wiz->lane_phy_type[i] == PHY_TYPE_USB3) \
> > +                                             && wiz->lane_phy_reg[i] == 0) {
> > +                                     regmap_field_write(wiz->typec_ln10_swap, 1);
> > +                             }
> > +                     }
>
> I really don't understand what you are doing here.
> It definitely doesn't match your comment.
> As an example. If num_lanes = 2 then wiz->lane_phy_reg[1] is being used without being
> really initialized (see later). Just because of kzalloc, it would of course be 0.
This register is used to configure the external lanes selections that
need to be swapped for SerDes type C. The initialization of the lanes
is done separately. This bit is set to configure that all control for
lane 0 will apply to lane 1 and vice versa.  Will update the commit
description.
>
> > +             }
> >       }
> >
> >       if (id == 0) {
> > @@ -1370,8 +1385,10 @@ static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz)
> >               dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__,
> >                       reg, reg + num_lanes - 1, phy_type);
> >
> > -             for (i = reg; i < reg + num_lanes; i++)
> > +             for (i = reg; i < reg + num_lanes; i++) {
> > +                     wiz->lane_phy_reg[i] = reg;
>
> As per DT binding
>       reg:
>         description:
>           The master lane number. This is the lowest numbered lane in the lane group.
>
> So you are in fact storing the Master lane number of every Link (or lane group).
> A link may have 1 or more lanes in it.
>
> Also notice that if num_lanes has been 2 then wiz->lane_phy_reg[1] is not initialized.
Irrespective of the number of lanes that are connected to the link, if
the master lane is '0' or '2'  and the PHY type is USB3, then this bit
needs to be set in the SerDes WIZ control register (according to the
design).
>
> >                       wiz->lane_phy_type[i] = phy_type;
> > +             }
> >       }
> >
> >       return 0;
> > @@ -1464,24 +1481,22 @@ static int wiz_probe(struct platform_device *pdev)
> >               goto err_addr_to_resource;
> >       }
> >
> > -     if (wiz->gpio_typec_dir) {
> > -             ret = of_property_read_u32(node, "typec-dir-debounce-ms",
> > -                                        &wiz->typec_dir_delay);
> > -             if (ret && ret != -EINVAL) {
> > -                     dev_err(dev, "Invalid typec-dir-debounce property\n");
> > -                     goto err_addr_to_resource;
> > -             }
> > +     ret = of_property_read_u32(node, "typec-dir-debounce-ms",
> > +                                &wiz->typec_dir_delay);
> > +     if (ret && ret != -EINVAL) {
> > +             dev_err(dev, "Invalid typec-dir-debounce property\n");
> > +             goto err_addr_to_resource;
> > +     }
> >
> > -             /* use min. debounce from Type-C spec if not provided in DT  */
> > -             if (ret == -EINVAL)
> > -                     wiz->typec_dir_delay = WIZ_TYPEC_DIR_DEBOUNCE_MIN;
> > +     /* use min. debounce from Type-C spec if not provided in DT  */
> > +     if (ret == -EINVAL)
> > +             wiz->typec_dir_delay = WIZ_TYPEC_DIR_DEBOUNCE_MIN;
> >
> > -             if (wiz->typec_dir_delay < WIZ_TYPEC_DIR_DEBOUNCE_MIN ||
> > -                 wiz->typec_dir_delay > WIZ_TYPEC_DIR_DEBOUNCE_MAX) {
> > -                     ret = -EINVAL;
> > -                     dev_err(dev, "Invalid typec-dir-debounce property\n");
> > -                     goto err_addr_to_resource;
> > -             }
> > +     if (wiz->typec_dir_delay < WIZ_TYPEC_DIR_DEBOUNCE_MIN ||
> > +         wiz->typec_dir_delay > WIZ_TYPEC_DIR_DEBOUNCE_MAX) {
> > +             ret = -EINVAL;
> > +             dev_err(dev, "Invalid typec-dir-debounce property\n");
> > +             goto err_addr_to_resource;
> >       }
> >
> >       ret = wiz_get_lane_phy_types(dev, wiz);
>
> cheers,
> -roger



-- 
With Regards
Sinthu Raja