Re: [PATCH v3 08/11] dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator

From: Conor Dooley
Date: Tue Dec 20 2022 - 18:19:17 EST


On Tue, Dec 20, 2022 at 08:50:51AM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@xxxxxxxx>
>
> Add bindings for the always-on clock and reset generator (AONCRG) on the
> JH7110 RISC-V SoC by StarFive Ltd.
>
> Signed-off-by: Emil Renner Berthing <kernel@xxxxxxxx>
> Signed-off-by: Hal Feng <hal.feng@xxxxxxxxxxxxxxxx>
> ---
> .../clock/starfive,jh7110-aoncrg.yaml | 76 +++++++++++++++++++
> .../dt-bindings/clock/starfive,jh7110-crg.h | 18 +++++
> .../dt-bindings/reset/starfive,jh7110-crg.h | 12 +++
> 3 files changed, 106 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml
> new file mode 100644
> index 000000000000..a3cf0570d950
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml
> @@ -0,0 +1,76 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7110 Always-On Clock and Reset Generator
> +
> +maintainers:
> + - Emil Renner Berthing <kernel@xxxxxxxx>
> +
> +properties:
> + compatible:
> + const: starfive,jh7110-aoncrg
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: Main Oscillator (24 MHz)
> + - description: RTC Oscillator (32.768 kHz)
> + - description: GMAC0 RMII reference
> + - description: GMAC0 RGMII RX

Gotta ask the same question here about the muxing - are all of these
clocks truly required?

> + - description: STG AXI/AHB
> + - description: APB Bus
> + - description: GMAC0 GTX
> +
> + clock-names:
> + items:
> + - const: osc
> + - const: rtc_osc
> + - const: gmac0_rmii_refin
> + - const: gmac0_rgmii_rxin
> + - const: stg_axiahb
> + - const: apb_bus
> + - const: gmac0_gtxclk

And if they are, is this actually needed since the order must be as
above?

As I said in the previous patch, I've probably missed something...

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