Re: [PATCH v1] clk: qcom: gcc-sc8280xp: add cxo as parent for gcc_ufs_ref_clkref_clk

[Bjorn Andersson]

On Thu, Nov 03, 2022 at 10:06:20AM +0100, Johan Hovold wrote:
> On Wed, Nov 02, 2022 at 09:49:49PM -0500, Bjorn Andersson wrote:
> > On Wed, Nov 02, 2022 at 10:26:13AM +0100, Johan Hovold wrote:
> > > On Wed, Nov 02, 2022 at 02:15:26PM +0530, Shazad Hussain wrote:
> > > > On 11/2/2022 1:43 PM, Johan Hovold wrote:
> > > 
> > > > > Right, but if the PHYs really requires CX and it is not an ancestor of
> > > > > the refclk then this should be described by the binding (and not be
> > > > > hidden away in the clock driver).
> > > 
> > > > This makes sense, will be posting v2 post for the same.
> > > > I assume this should use the Fixes tag then !
> > > 
> > > Yeah, I guess to you can add a fixes tag for the commits adding support
> > > for sc8280xp to the UFS PHY binding and driver.
> > > 
> > > But please do check with the hardware documentation first so we get this
> > > right this time.
> > > 
> > > I've already asked Bjorn to see what he can dig out as it is still not
> > > clear how the two "card" refclocks (GCC_UFS_CARD_CLKREF_CLK and
> > > GCC_UFS_1_CARD_CLKREF_CLK) are supposed to be used.
> > > 
> > 
> > We've come full circle and Shazad's patch came from that discussion :)
> 
> Ah, good. :)
> 
> > In line with the downstream dts, we have GCC_UFS{,_1}_CARD_CLKREF_CLK
> > providing a reference clock to the two phys. Then GCC_UFS_REF_CLKREF_CLK
> > feeds the UFS refclock pads (both of them), which connect to the memory
> > device(s).
> > 
> > In other words, GCC_UFS{,_1}_CARD_CLKREF_CLK should be "ref" in
> > respective phy.
> > 
> > GCC_UFS_REF_CLKREF_CLK is the clock to the devices, but as we don't
> > represent the memory device explicitly it seems suitable to use as
> > "ref_clk" in the ufshc nodes - which would then match the special
> > handling of the "link clock" in the UFS driver.
> 
> Thanks for clearing that up. Using GCC_UFS_REF_CLKREF_CLK as ref_clk for
> the controller sounds reasonable.
> 
> I guess the only missing piece is which "card" ref clock is used by
> which PHY.
> 
> The ADP dts uses:
> 
> 	phy			ref clock
> 
> 	phy@1d87000 (UFS_PHY)	GCC_UFS_CARD_CLKREF_CLK
> 	phy@1da7000 (UFS_CARD)	GCC_UFS_1_CARD_CLKREF_CLK
> 

This matches the documentation.

Regards,
Bjorn

> but that is not what the firmware on ADP and CRD seem to enable.
> 
> Both the ADP and CRD fw leaves GCC_UFS_1_CARD_CLKREF_CLK enabled, while
> GCC_UFS_CARD_CLKREF_CLK is only enabled on ADP (which unlike the CRD
> also uses the UFS_CARD controller).
> 
> Does the ADP dts have these clocks switched or is the firmware confused?
> 
> (Also note that experiments suggest that neither refclock appears to
> has to be explicitly enabled for the controllers to function.)
> 
> > All three clocks are sourced off the CXO pad, so I would like this patch
> > to cover at least all of these. And
> > 
> > Fixes: d65d005f9a6c ("clk: qcom: add sc8280xp GCC driver")
> > 
> > seems to be in order for such patch.
> > 
> > 
> > @Johan, would you mind writing a dts patch flipping the clocks around
> > and Shazad can update this patch?
> 
> I'll do so, but I'll wait with posting until you can confirm which
> clkref is which.
> 
> Johan