RE: [PATCH 20/20] arm64: dts: Update cache properties for tesla

[Alim Akhtar]

>-----Original Message-----
>From: Pierre Gondois [mailto:pierre.gondois@xxxxxxx]
>Sent: Monday, October 31, 2022 2:51 PM
>To: linux-kernel@xxxxxxxxxxxxxxx
>Cc: pierre.gondois@xxxxxxx; Rob.Herring@xxxxxxx; Rob Herring
><robh+dt@xxxxxxxxxx>; Krzysztof Kozlowski
><krzysztof.kozlowski+dt@xxxxxxxxxx>; Alim Akhtar
><alim.akhtar@xxxxxxxxxxx>; Aswani Reddy <aswani.reddy@xxxxxxxxxxx>;
>Shashank Prashar <s.prashar@xxxxxxxxxxx>; Sriranjani P
><sriranjani.p@xxxxxxxxxxx>; devicetree@xxxxxxxxxxxxxxx
>Subject: [PATCH 20/20] arm64: dts: Update cache properties for tesla
>
>The DeviceTree Specification v0.3 specifies that the cache node
'compatible'
>and 'cache-level' properties are 'required'. Cf.
>s3.8 Multi-level and Shared Cache Nodes
>
>The recently added init_of_cache_level() function checks these properties.
>Add them if missing.
>
>Signed-off-by: Pierre Gondois <pierre.gondois@xxxxxxx>
>---
Reviewed-by: Alim Akhtar <alim.akhtar@xxxxxxxxxxx>


> arch/arm64/boot/dts/tesla/fsd.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
>diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi
>b/arch/arm64/boot/dts/tesla/fsd.dtsi
>index f35bc5a288c2..bfab040fc1e4 100644
>--- a/arch/arm64/boot/dts/tesla/fsd.dtsi
>+++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
>@@ -284,6 +284,7 @@ cpucl_l2: l2-cache0 {
> 			cache-size = <0x400000>;
> 			cache-line-size = <64>;
> 			cache-sets = <4096>;
>+			cache-level = <2>;
> 		};
>
> 		idle-states {
>--
>2.25.1