[esmil:visionfive 22/42] drivers/soc/sifive/sifive_l2_cache.c:285:17: error: implicit declaration of function 'riscv_noncoherent_supported'

[kernel test robot]

tree:   https://github.com/esmil/linux visionfive
head:   044c1f5e968de7d30940431fbb90da599074ea1c
commit: 481ec6aefdf9cbaae1dd26f65aea0ace44b4a335 [22/42] soc: sifive: l2 cache: Add non-coherent DMA handling
config: riscv-randconfig-r002-20220907 (https://download.01.org/0day-ci/archive/20220910/202209100507.S5XBgELa-lkp@xxxxxxxxx/config)
compiler: riscv32-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/esmil/linux/commit/481ec6aefdf9cbaae1dd26f65aea0ace44b4a335
        git remote add esmil https://github.com/esmil/linux
        git fetch --no-tags esmil visionfive
        git checkout 481ec6aefdf9cbaae1dd26f65aea0ace44b4a335
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=riscv SHELL=/bin/bash

If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@xxxxxxxxx>

All errors (new ones prefixed by >>):

   drivers/soc/sifive/sifive_l2_cache.c: In function 'sifive_l2_init':
>> drivers/soc/sifive/sifive_l2_cache.c:285:17: error: implicit declaration of function 'riscv_noncoherent_supported' [-Werror=implicit-function-declaration]
     285 |                 riscv_noncoherent_supported();
         |                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~
   cc1: some warnings being treated as errors


vim +/riscv_noncoherent_supported +285 drivers/soc/sifive/sifive_l2_cache.c

   240	
   241	static int __init sifive_l2_init(void)
   242	{
   243		struct device_node *np;
   244		struct resource res;
   245		int i, rc, intr_num;
   246		const struct of_device_id *match;
   247		unsigned long broken_irqs;
   248		u64 offset;
   249	
   250		np = of_find_matching_node_and_match(NULL, sifive_l2_ids, &match);
   251		if (!np)
   252			return -ENODEV;
   253	
   254		broken_irqs = (uintptr_t)match->data;
   255	
   256		if (of_address_to_resource(np, 0, &res))
   257			return -ENODEV;
   258	
   259		l2_base = ioremap(res.start, resource_size(&res));
   260		if (!l2_base)
   261			return -ENOMEM;
   262	
   263		intr_num = of_property_count_u32_elems(np, "interrupts");
   264		if (!intr_num) {
   265			pr_err("L2CACHE: no interrupts property\n");
   266			return -ENODEV;
   267		}
   268	
   269		for (i = 0; i < intr_num; i++) {
   270			g_irq[i] = irq_of_parse_and_map(np, i);
   271	
   272			if (broken_irqs & BIT(i))
   273				continue;
   274	
   275			rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL);
   276			if (rc) {
   277				pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]);
   278				return rc;
   279			}
   280		}
   281	
   282		if (!of_property_read_u64(np, "uncached-offset", &offset)) {
   283			uncached_offset = offset;
   284			static_branch_enable(&sifive_l2_handle_noncoherent_key);
 > 285			riscv_noncoherent_supported();
   286		}
   287	
   288		l2_config_read();
   289	
   290		l2_cache_ops.get_priv_group = l2_get_priv_group;
   291		riscv_set_cacheinfo_ops(&l2_cache_ops);
   292	

-- 
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