Re: [PATCH v2 9/9] perf/x86/intel: Optimize short PEBS counters

[Peter Zijlstra]

On Mon, Aug 29, 2022 at 11:55:12AM -0400, Liang, Kan wrote:
> 
> 
> On 2022-08-29 6:10 a.m., Peter Zijlstra wrote:
> > XXX: crazy idea; really not sure this is worth the extra complexity
> > 
> > It is possible to have the counter programmed to a value smaller than
> > the sampling period.
> 
> I'm not quite sure how the above case can be triggered.
> 
> For the most of the cases, the pmc_prev_left[idx] should be the same as
> the hwc->period_left.
> 
> For the left < 2 or the limit_period case, I think perf usually program
> a larger value, so the pmc_prev_left[idx] > hwc->period_left.
> 
> It looks like the only case, which triggers the pmc_prev_left[idx] <
> hwc->period_left, is the left > max_period. I don't think it's common
> for a user to set a period which is larger than the HW counter limit.
> Even if they set a huge period, the PEBS overhead should not be an
> issue, since it may causes days to trigger a sample.
> 
> If so, it may not be a good idea to introduce such complexity to only
> handle such rare cases.

Yeah, happy to forget this patch exists.. I wrote this things months ago
and I'm not entirely sure why :-)