I definitely don't think I 100% understand all the ordering things sinceAtomicity doesn't guarantee ordering, unfortunately. Take the
they're complicated.. but my understanding is that the reset procedure
didn't need memory barrier (unlike pushing, where we have explicit wmb),
because we assumed the userapp is not hostile so logically it should only
modify the flags which is a 32bit field, assuming atomicity guaranteed.
following example: CPU0 is changing a bunch of flags for GFNs A, B, C,
D that exist in the ring in that order, and CPU1 performs an ioctl to
reset the page state.
CPU0:
write_flag(A, KVM_DIRTY_GFN_F_RESET)
write_flag(B, KVM_DIRTY_GFN_F_RESET)
write_flag(C, KVM_DIRTY_GFN_F_RESET)
write_flag(D, KVM_DIRTY_GFN_F_RESET)
[...]
CPU1:
ioctl(KVM_RESET_DIRTY_RINGS)
Since CPU0 writes do not have any ordering, CPU1 can observe the
writes in a sequence that have nothing to do with program order, and
could for example observe that GFN A and D have been reset, but not B
and C. This in turn breaks the logic in the reset code (B, C, and D
don't get reset), despite userspace having followed the spec to the
letter. If each was a store-release (which is the case on x86), it
wouldn't be a problem, but nothing calls it in the documentation.
Maybe that's not a big deal if it is expected that each CPU will issue
a KVM_RESET_DIRTY_RINGS itself, ensuring that it observe its own
writes. But expecting this to work across CPUs without any barrier is
wishful thinking.