Re: [PATCH] MIPS: smp-mt: enable all hardware interrupts on second VPE

[Thomas Bogendoerfer]

On Thu, Jul 28, 2022 at 05:50:10PM +0200, Martin Blumenstingl wrote:
> I think for the Realtek SoC's this would be problematic because it's
> using MIPS_GENERIC. My understanding is that in an ideal world all

which SOC are these ?

> platforms would switch to MIPS_GENERIC.
> As an alternative to making irq-mips-cpu capable of changing another
> CPU's registers: would you also be happy with a change that implements
> the following idea (pseudocode) in vsmp_init_secondary():
>     struct device_node *root_node = of_find_node_by_path("/");
> 
>     if (mips_gic_present() ||
>         of_device_is_compatible(root_node, "lantiq,xrx200") ||
>         of_device_is_compatible(root_node, "realtek,some-relevant-soc"))
>         change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 |
>             STATUSF_IP4 | STATUSF_IP5 |
>             STATUSF_IP6 | STATUSF_IP7);
>     else
>        ...
> 
>     of_node_put(root_node);
> 
> That way we don't risk enabling interrupt lines which shouldn't be
> enabled (on SoCs which we don't know).
> And also it would not cause any issues with MIPS_GENERIC support.

well it's not exactly the abstraction I'm looking for, but it's ok for me
as a short term way to move forward.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]