Re: [PATCH v2] x86/resctrl: Fix zero cbm for AMD in cbm_validate

[Moger, Babu]

On 7/25/22 14:47, Babu Moger wrote:
> Subject: Re: [PATCH v2] x86/resctrl: Fix zero cbm for AMD in cbm_validate
>
> Sorry, I didn't see this thread. Just noticed going thru the archives.
> Replying using "git send-email" to the thread.
>  
> Thanks Stephane for the patch. Thanks Fenghua and Reinette for your comments.
>  
> Stephane, Are you planning to re-submit the patch with Fenghua's proposal?
> If not I will resubmit with my current patch-set.

Didn't see Stephan's response yet. I will add this patch in my QoS series.

Stephan, Let me know if you want me to add your "Signed-off-by".

Thanks

Babu

>  
> I agree with Fenghua's proposal. Here is my proposal with slight modification.
>  
> Thanks 
>
> ==================================================================================
>
> Subject: Re: [PATCH v2] x86/resctrl: Fix zero cbm for AMD in cbm_validate
>
> Signed-off-by: Babu Moger <babu.moger@xxxxxxx>
>
>
> diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c
> index bb1c3f5f60c8..a5c51a14fbce 100644
> --- a/arch/x86/kernel/cpu/resctrl/core.c
> +++ b/arch/x86/kernel/cpu/resctrl/core.c
> @@ -66,9 +66,6 @@ struct rdt_hw_resource rdt_resources_all[] = {
>  			.rid			= RDT_RESOURCE_L3,
>  			.name			= "L3",
>  			.cache_level		= 3,
> -			.cache = {
> -				.min_cbm_bits	= 1,
> -			},
>  			.domains		= domain_init(RDT_RESOURCE_L3),
>  			.parse_ctrlval		= parse_cbm,
>  			.format_str		= "%d=%0*x",
> @@ -83,9 +80,6 @@ struct rdt_hw_resource rdt_resources_all[] = {
>  			.rid			= RDT_RESOURCE_L2,
>  			.name			= "L2",
>  			.cache_level		= 2,
> -			.cache = {
> -				.min_cbm_bits	= 1,
> -			},
>  			.domains		= domain_init(RDT_RESOURCE_L2),
>  			.parse_ctrlval		= parse_cbm,
>  			.format_str		= "%d=%0*x",
> @@ -877,6 +871,7 @@ static __init void rdt_init_res_defs_intel(void)
>  			r->cache.arch_has_sparse_bitmaps = false;
>  			r->cache.arch_has_empty_bitmaps = false;
>  			r->cache.arch_has_per_cpu_cfg = false;
> +			r->cache.min_cbm_bits = 1;
>  		} else if (r->rid == RDT_RESOURCE_MBA) {
>  			hw_res->msr_base = MSR_IA32_MBA_THRTL_BASE;
>  			hw_res->msr_update = mba_wrmsr_intel;
> @@ -897,6 +892,7 @@ static __init void rdt_init_res_defs_amd(void)
>  			r->cache.arch_has_sparse_bitmaps = true;
>  			r->cache.arch_has_empty_bitmaps = true;
>  			r->cache.arch_has_per_cpu_cfg = true;
> +			r->cache.min_cbm_bits = 0;
>  		} else if (r->rid == RDT_RESOURCE_MBA) {
>  			hw_res->msr_base = MSR_IA32_MBA_BW_BASE;
>  			hw_res->msr_update = mba_wrmsr_amd;

-- 
Thanks
Babu Moger