RE: [PATCH v6 0/2] Add support for Xilinx Versal CPM5 Root Port

[Gogada, Bharat Kumar]

Ping!

> -----Original Message-----
> From: Bharat Kumar Gogada <bharat.kumar.gogada@xxxxxxxxxx>
> Sent: Tuesday, July 5, 2022 4:27 PM
> To: linux-pci@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx
> Cc: bhelgaas@xxxxxxxxxx; michals@xxxxxxxxxx; Bharat Kumar Gogada
> <bharat.kumar.gogada@xxxxxxxxxx>
> Subject: [PATCH v6 0/2] Add support for Xilinx Versal CPM5 Root Port
> 
> Xilinx Versal Premium series has CPM5 block which supports Root Port
> functioning at Gen5 speed.
> 
> Xilinx Versal CPM5 has few changes with existing CPM block.
> - CPM5 has dedicated register space for control and status registers.
> - CPM5 legacy interrupt handling needs additional register bit
>   to enable and handle legacy interrupts.
> 
> Changes in v6:
> - Added of_device_get_match_data to identify CPM version.
> - Used enum values to differentiate CPM version.
> 
> Bharat Kumar Gogada (2):
>   dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port
>   PCI: xilinx-cpm: Add support for Versal CPM5 Root Port
> 
>  .../bindings/pci/xilinx-versal-cpm.yaml       | 38 ++++++++++-
>  drivers/pci/controller/pcie-xilinx-cpm.c      | 64 ++++++++++++++++++-
>  2 files changed, 98 insertions(+), 4 deletions(-)
> 
> --
> 2.17.1