[irqchip: irq/irqchip-next] irqchip/gic-v3: Fix comment typo

From: irqchip-bot for Jason Wang
Date: Tue Jul 19 2022 - 07:21:20 EST


The following commit has been merged into the irq/irqchip-next branch of irqchip:

Commit-ID: 295171705c9ac98f4626609033f6bab0c2e37ed0
Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/295171705c9ac98f4626609033f6bab0c2e37ed0
Author: Jason Wang <wangborong@xxxxxxxxxx>
AuthorDate: Fri, 15 Jul 2022 13:12:58 +08:00
Committer: Marc Zyngier <maz@xxxxxxxxxx>
CommitterDate: Tue, 19 Jul 2022 12:13:31 +01:00

irqchip/gic-v3: Fix comment typo

The double `the' is duplicated in line 1786, remove one.

Signed-off-by: Jason Wang <wangborong@xxxxxxxxxx>
Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx>
Link: https://lore.kernel.org/r/20220715051258.28889-1-wangborong@xxxxxxxxxx
---
drivers/irqchip/irq-gic-v3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index 5c1cf90..d28b45f 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -1783,7 +1783,7 @@ static void gic_enable_nmi_support(void)
* the security state of the GIC (controlled by the GICD_CTRL.DS bit)
* and if Group 0 interrupts can be delivered to Linux in the non-secure
* world as FIQs (controlled by the SCR_EL3.FIQ bit). These affect the
- * the ICC_PMR_EL1 register and the priority that software assigns to
+ * ICC_PMR_EL1 register and the priority that software assigns to
* interrupts:
*
* GICD_CTRL.DS | SCR_EL3.FIQ | ICC_PMR_EL1 | Group 1 priority