Re: [PATCH 06/43] dt-bindings: phy: qcom,qmp: split out msm8996-qmp-pcie-phy

[Krzysztof Kozlowski]

On 05/07/2022 11:42, Johan Hovold wrote:
> The QMP PHY DT schema is getting unwieldy. Break out the odd-bird
> msm8996-qmp-pcie-phy which is the only QMP PHY that uses separate
> "per-lane" nodes.
> 
> Signed-off-by: Johan Hovold <johan+linaro@xxxxxxxxxx>
> ---
>  .../phy/qcom,msm8996-qmp-pcie-phy.yaml        | 114 ++++++++++++++++++
>  .../devicetree/bindings/phy/qcom,qmp-phy.yaml |  32 -----
>  2 files changed, 114 insertions(+), 32 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-pcie-phy.yaml
> 
> diff --git a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-pcie-phy.yaml
> new file mode 100644
> index 000000000000..14fd86fd91ec
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-pcie-phy.yaml
> @@ -0,0 +1,114 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +

No line break

> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/phy/qcom,msm8996-qmp-pcie-phy.yaml#";
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#";

Drop the quotes from two above.

> +
> +title: Qualcomm QMP PHY controller (MSM8996 PCIe)
> +
> +maintainers:
> +  - Vinod Koul <vkoul@xxxxxxxxxx>
> +
> +description:
> +  QMP PHY controller supports physical layer functionality for a number of
> +  controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
> +
> +properties:
> +  compatible:
> +    const: qcom,msm8996-qmp-pcie-phy
> +
> +  reg:
> +    minItems: 1
> +    items:
> +      - description: Address and length of PHY's common serdes block.
> +      - description: Address and length of PHY's DP_COM control block.

Are two reg items applicable here?

> +
> +  "#address-cells":
> +    enum: [ 1, 2 ]
> +
> +  "#size-cells":
> +    enum: [ 1, 2 ]
> +
> +  ranges: true
> +
> +  clocks:
> +    minItems: 1
> +    maxItems: 4

Define clocks here, not in allOf:if:then.

> +
> +  clock-names:
> +    minItems: 1
> +    maxItems: 4

Ditto

> +
> +  resets:
> +    minItems: 1
> +    maxItems: 3

Ditto

> +
> +  reset-names:
> +    minItems: 1
> +    maxItems: 3

Ditto

> +
> +  vdda-phy-supply:
> +    description:
> +      Phandle to a regulator supply to PHY core block.
> +
> +  vdda-pll-supply:
> +    description:
> +      Phandle to 1.8V regulator supply to PHY refclk pll block.
> +
> +  vddp-ref-clk-supply:
> +    description:
> +      Phandle to a regulator supply to any specific refclk pll block.
> +
> +patternProperties:
> +  "^phy@[0-9a-f]+$":
> +    type: object
> +    description:
> +      Each device node of QMP PHY is required to have as many child nodes as
> +      the number of lanes the PHY has.
> +
> +required:
> +  - compatible
> +  - reg
> +  - "#address-cells"
> +  - "#size-cells"
> +  - ranges
> +  - clocks
> +  - clock-names
> +  - resets
> +  - reset-names
> +
> +additionalProperties: false
> +
> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - qcom,msm8996-qmp-pcie-phy
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: PHY aux clock.
> +            - description: PHY config clock.
> +            - description: 19.2 MHz ref clock.
> +        clock-names:
> +          items:
> +            - const: aux
> +            - const: cfg_ahb
> +            - const: ref
> +        resets:
> +          items:
> +            - description: Reset of PHY block.
> +            - description: PHY common block reset.
> +            - description: PHY's ahb cfg block reset.
> +        reset-names:
> +          items:
> +            - const: phy
> +            - const: common
> +            - const: cfg
> +      required:
> +        - vdda-phy-supply
> +        - vdda-pll-supply

How about an example?


Best regards,
Krzysztof