RE: [V2] tty: serial: qcom-geni-serial: Fix get_clk_div_rate() which otherwise could return a sub-optimal clock rate.

[Vijaya Krishna Nivarthi (Temp)]

Hi,


> -----Original Message-----
> From: Doug Anderson <dianders@xxxxxxxxxxxx>
> Sent: Friday, July 1, 2022 8:38 PM
> To: Vijaya Krishna Nivarthi (Temp) (QUIC) <quic_vnivarth@xxxxxxxxxxx>
> Cc: Andy Gross <agross@xxxxxxxxxx>; bjorn.andersson@xxxxxxxxxx; Konrad
> Dybcio <konrad.dybcio@xxxxxxxxxxxxxx>; Greg Kroah-Hartman
> <gregkh@xxxxxxxxxxxxxxxxxxx>; Jiri Slaby <jirislaby@xxxxxxxxxx>; linux-arm-
> msm <linux-arm-msm@xxxxxxxxxxxxxxx>; linux-serial@xxxxxxxxxxxxxxx; LKML
> <linux-kernel@xxxxxxxxxxxxxxx>; Mukesh Savaliya (QUIC)
> <quic_msavaliy@xxxxxxxxxxx>; Matthias Kaehlcke <mka@xxxxxxxxxxxx>;
> Stephen Boyd <swboyd@xxxxxxxxxxxx>
> Subject: Re: [V2] tty: serial: qcom-geni-serial: Fix get_clk_div_rate() which
> otherwise could return a sub-optimal clock rate.
> 
> WARNING: This email originated from outside of Qualcomm. Please be wary
> of any links or attachments, and do not enable macros.
> 
> Hi,
> 
> On Fri, Jul 1, 2022 at 4:04 AM Vijaya Krishna Nivarthi (Temp) (QUIC)
> <quic_vnivarth@xxxxxxxxxxx> wrote:
> >
> > Hi,
> >
> >
> > > -----Original Message-----
> > > From: Doug Anderson <dianders@xxxxxxxxxxxx>
> > > Sent: Thursday, June 30, 2022 4:45 AM
> > > To: Vijaya Krishna Nivarthi (Temp) (QUIC)
> > > <quic_vnivarth@xxxxxxxxxxx>
> > > Cc: Andy Gross <agross@xxxxxxxxxx>; bjorn.andersson@xxxxxxxxxx;
> > > Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxx>; Greg Kroah-Hartman
> > > <gregkh@xxxxxxxxxxxxxxxxxxx>; Jiri Slaby <jirislaby@xxxxxxxxxx>;
> > > linux-arm- msm <linux-arm-msm@xxxxxxxxxxxxxxx>;
> > > linux-serial@xxxxxxxxxxxxxxx; LKML <linux-kernel@xxxxxxxxxxxxxxx>;
> > > Mukesh Savaliya (QUIC) <quic_msavaliy@xxxxxxxxxxx>; Matthias
> > > Kaehlcke <mka@xxxxxxxxxxxx>; Stephen Boyd
> <swboyd@xxxxxxxxxxxx>
> > > Subject: Re: [V2] tty: serial: qcom-geni-serial: Fix
> > > get_clk_div_rate() which otherwise could return a sub-optimal clock rate.
> > >
> > >
> > >
> > > > +                               /* Save the first (lowest freq) within tolerance */
> > > > +                               ser_clk = freq;
> > > > +                               *clk_div = new_div;
> > > > +                               /* no more search for exact match required in 2nd run
> */
> > > > +                               if (!exact_match)
> > > > +                                       break;
> > > > +                       }
> > > > +               }
> > > >
> > > > -               prev = freq;
> > > > +               div = freq / desired_clk + 1;
> > >
> > > Can't you infinite loop now?
> > >
> > > Start with:
> > >
> > > desired_clk = 10000
> > > div = 1
> > > percent_tol = 2
> > >
> > >
> > > Now:
> > >
> > > mult = 10000
> > > offset = 200
> > > test_freq = 9800
> > > freq = 9800
> > > div = 9800 / 10000 + 1 = 0 + 1 = 1
> > >
> > > ...and then you'll loop again with "div = 1", won't you? ...or did I
> > > get something wrong in my analysis? This is the reason my proposed
> > > algorithm had two loops.
> > >
> > >
> >
> > I went back to your proposed algorithm and made couple of simple
> changes, and it seemed like what we need.
> >
> > a) look only for exact match once a clock rate within tolerance is
> > found
> > b) swap test_freq and freq at end of while loops to make it run as
> > desired
> >
> >
> >         maxdiv = CLK_DIV_MSK >> CLK_DIV_SHFT;
> >         div = 1;
> >
> >         while (div < maxdiv) {
> >                 mult = (unsigned long long)div * desired_clk;
> >                 if (mult != (unsigned long)mult)
> >                         break;
> >
> >                 if (ser_clk)
> >                         offset = 0;
> >                 ===================a=====================
> >                 else
> >                         offset = div_u64(mult * percent_tol, 100);
> >
> >                 /*
> >                  * Loop requesting (freq - 2%) and possibly (freq).
> >                  *
> >                  * We'll keep track of the lowest freq inexact match we found
> >                  * but always try to find a perfect match. NOTE: this algorithm
> >                  * could miss a slightly better freq if there's more than one
> >                  * freq between (freq - 2%) and (freq) but (freq) can't be made
> >                  * exactly, but that's OK.
> >                  *
> >                  * This absolutely relies on the fact that the Qualcomm clock
> >                  * driver always rounds up.
> >                  */
> >                 test_freq = mult - offset;
> >                 while (test_freq <= mult) {
> >                         freq = clk_round_rate(clk, test_freq);
> >
> >                         /*
> >                          * A dead-on freq is an insta-win. This implicitly
> >                          * handles when "freq == mult"
> >                          */
> >                         if (!(freq % desired_clk)) {
> >                                 *clk_div = freq / desired_clk;
> >                                 return freq;
> >                         }
> >
> >                         /*
> >                          * Only time clock framework doesn't round up is if
> >                          * we're past the max clock rate. We're done searching
> >                          * if that's the case.
> >                          */
> >                         if (freq < test_freq)
> >                                 return ser_clk;
> >
> >                         /* Save the first (lowest freq) within tolerance */
> >                         if (!ser_clk && freq <= mult + offset) {
> >                                 ser_clk = freq;
> >                                 *clk_div = div;
> >                         }
> >
> >                         /*
> >                          * If we already rounded up past mult then this will
> >                          * cause the loop to exit. If not then this will run
> >                          * the loop a second time with exactly mult.
> >                          */
> >                         test_freq = max(test_freq + 1, mult);
> >                                                      ====b====
> >                 }
> >
> >                 /*
> >                  * freq will always be bigger than mult by at least 1.
> >                  * That means we can get the next divider with a DIV_ROUND_UP.
> >                  * This has the advantage of skipping by a whole bunch of divs
> >                  * If the clock framework already bypassed them.
> >                  */
> >                 div = DIV_ROUND_UP(freq, desired_clk);
> >                                                        ===b==
> >         }
> >
> >
> > Will also drop exact_match now.
> >
> > Will upload v3 after testing.
> 
> The more I've been thinking about it, the more I wonder if we even need the
> special case of looking for an exact match at all. It feels like we should choose
> one: we either look for the best match or we look for the one with the
> lowest clock source rate. The weird half-half approach that we have right
> now feels like over-engineering and complicates things.
> 
> How about this (again, only lightly tested). Worst case if we _truly_ need a
> close-to-exact match we could pass a tolerance of 0 in and we'd get
> something that's nearly exact, though I'm not suggesting we actually do that.
> If we think 2% is good enough then we should just accept the first (and
> lowest clock rate) 2% match we find.
> 
>     abs_tol = div_u64((u64)desired_clk * percent_tol, 100);
>     maxdiv = CLK_DIV_MSK >> CLK_DIV_SHFT;
>     div = 1;
>     while (div <= maxdiv) {
>         mult = (u64)div * desired_clk;
>         if (mult != (unsigned long)mult)
>             break;
> 
>         offset = div * abs_tol;
>         freq = clk_round_rate(clk, mult - offset);
> 
>         /* Can only get lower if we're done */
>         if (freq < mult - offset)
>             break;
> 
>         /*
>          * Re-calculate div in case rounding skipped rates but we
>          * ended up at a good one, then check for a match.
>          */
>         div = DIV_ROUND_CLOSEST(freq, desired_clk);
>         achieved = DIV_ROUND_CLOSEST(freq, div);
>         if (achieved <= desired_clk + abs_tol &&
>             achieved >= desired_clk - abs_tol) {
>             *clk_div = div;
>             return freq;
>         }
> 
>         /*
>          * Always increase div by at least one, but we'll go more than
>          * one if clk_round_rate() gave us something higher.
>          */
>         div = DIV_ROUND_UP(max(freq, (unsigned long)mult) + 1, desired_clk);

Wouldn’t DIV_ROUND_UP(freq, desired_clk) suffice here?
freq >= mult-offset, else we would have hit break.
Additionally if freq <= mult we would have hit return.
So always freq > mult?

And hence div++ would do the same?

Thank you.



>         }
> 
>     return 0;