Re: [PATCH] kvm: x86/svm/nested: Cache PDPTEs for nested NPT in PAE paging mode

[Paolo Bonzini]

On 5/26/22 10:38, Lai Jiangshan wrote:
> > (Although the APM does say that "modern processors" do not pre-load
> > PDPTEs.)

This changed between the Oct 2020 and Nov 2021, so I suppose the change 
was done in Zen 3.

> Oh, I also missed the fact that L1 is the host when emulating it.
>
> The code is for host-mode (L1)'s nested_cr3 which is using the
> traditional PAE PDPTEs loading and checking.
>
> So using caches is the only correct way, right?

The caching behavior for NPT PDPTEs does not matter too much.  What 
matters is that a PDPTE with reserved bits should cause a #NPF at usage 
time rather than a VMentry failure or a #NPF immediately after VMentry.

Paolo