Re: [PATCH V11 02/22] Documentation/zh_CN: Add basic LoongArch documentations

[WANG Xuerui]

Hi,

On 5/20/22 15:37, Guo Ren wrote:
> On Wed, May 18, 2022 at 5:27 PM Huacai Chen <chenhuacai@xxxxxxxxxxx> wrote:
> > [snip]
> >
> > +
> > +指令列表
> > +--------
> > +
> > +为了简便起见，我们在此只罗列一下指令名称（助记符），需要详细信息请阅读
> > +:ref:`参考文献 <loongarch-references-zh_CN>` 中的文档。
> > +
> > +1. 算术运算指令::
> > +
> > +    ADD.W SUB.W ADDI.W ADD.D SUB.D ADDI.D
> > +    SLT SLTU SLTI SLTUI
> > +    AND OR NOR XOR ANDN ORN ANDI ORI XORI
> > +    MUL.W MULH.W MULH.WU DIV.W DIV.WU MOD.W MOD.WU
> > +    MUL.D MULH.D MULH.DU DIV.D DIV.DU MOD.D MOD.DU
> > +    PCADDI PCADDU12I PCADDU18I
> > +    LU12I.W LU32I.D LU52I.D ADDU16I.D
> > +
> > +2. 移位运算指令::
> > +
> > +    SLL.W SRL.W SRA.W ROTR.W SLLI.W SRLI.W SRAI.W ROTRI.W
> > +    SLL.D SRL.D SRA.D ROTR.D SLLI.D SRLI.D SRAI.D ROTRI.D
> > +
> > +3. 位域操作指令::
> > +
> > +    EXT.W.B EXT.W.H CLO.W CLO.D SLZ.W CLZ.D CTO.W CTO.D CTZ.W CTZ.D
> > +    BYTEPICK.W BYTEPICK.D BSTRINS.W BSTRINS.D BSTRPICK.W BSTRPICK.D
> > +    REVB.2H REVB.4H REVB.2W REVB.D REVH.2W REVH.D BITREV.4B BITREV.8B BITREV.W BITREV.D
> > +    MASKEQZ MASKNEZ
> > +
> > +4. 分支转移指令::
> > +
> > +    BEQ BNE BLT BGE BLTU BGEU BEQZ BNEZ B BL JIRL
> > +
> > +5. 访存读写指令::
> > +
> > +    LD.B LD.BU LD.H LD.HU LD.W LD.WU LD.D ST.B ST.H ST.W ST.D
> > +    LDX.B LDX.BU LDX.H LDX.HU LDX.W LDX.WU LDX.D STX.B STX.H STX.W STX.D
> > +    LDPTR.W LDPTR.D STPTR.W STPTR.D
> > +    PRELD PRELDX
> > +
> > +6. 原子操作指令::
> > +
> > +    LL.W SC.W LL.D SC.D
> > +    AMSWAP.W AMSWAP.D AMADD.W AMADD.D AMAND.W AMAND.D AMOR.W AMOR.D AMXOR.W AMXOR.D
> > +    AMMAX.W AMMAX.D AMMIN.W AMMIN.D
> > +
> > +7. 栅障指令::
> > +
> > +    IBAR DBAR
> Is IBAR is pipeline flush? I think DBAR is for LSU fence. loongarch is
> weak consistency, right?
>
> I think we just leave DBAR here, and put IBAR into 8. Flush pipeline
> is not for memory consistency.
I believe he's just listing the instructions in the exact same 
organization as the ISA manual. LoongArch memory model is indeed weak, 
and IBAR most certainly just flushes the instruction fetch pipeline wrt. 
the memory stores happening in the same core (this is what the manual 
says, section 2.2.8.1).
> Overall, I give:
> Reviewed-by: Guo Ren <guoren@xxxxxxxxxx>