Re: [PATCH -next v2 1/3] RISC-V: add Bitmanip/Scalar Crypto parsing from DT

From: Conor.Dooley
Date: Wed May 18 2022 - 05:50:30 EST

On 18/05/2022 10:25, Hongren (Zenithal) Zheng wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> This commit parses Zb/Zk related string from DT and
> output them in cpuinfo

Similarly here, the typical "this patch" comment.

>
> One thing worth noting is that if DT provides zk,
> all zbkb, zbkc, zbkx and zkn, zkr, zkt would be enabled.
>
> Note that zk is a valid extension name and the current
> DT binding spec allows this.
>
> This commit also changes the logical id of

"also" makes it sound like this a separate change?
If so, split it into another patch.

> existing multi-letter extensions and adds a statement
> that instead of logical id compatibility, the order
> is needed.
>
> There currently lacks a mechanism to merge them when
> producing cpuinfo. Namely if you provide a riscv,isa
> "rv64imafdc_zk_zks", the cpuinfo output would be
> "rv64imafdc_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zksed
> _zksh_zkt"
>
> Tested-by: Jiatai He <jiatai2021@xxxxxxxxxxx>
> Signed-off-by: Hongren (Zenithal) Zheng <i@xxxxxxxxxxx>
> ---
> arch/riscv/include/asm/hwcap.h | 20 +++++++++++++++++++-
> arch/riscv/kernel/cpu.c | 14 ++++++++++++++
> arch/riscv/kernel/cpufeature.c | 33 +++++++++++++++++++++++++++++++++
> 3 files changed, 66 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index 4e2486881840..02c454a12683 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -49,9 +49,27 @@ extern unsigned long elf_hwcap;
> * RISCV_ISA_EXT_MAX. 0-25 range is reserved for single letter
> * extensions while all the multi-letter extensions should define the next
> * available logical extension id.
> + *
> + * The order of them should be maintained according to the riscv-isa-manual.
> + * As this is an internal API, changing the id of one extension does
> + * not affect compatibility.
> */
> enum riscv_isa_ext_id {
> - RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE,
> + RISCV_ISA_EXT_ZBA = RISCV_ISA_EXT_BASE,
> + RISCV_ISA_EXT_ZBB,
> + RISCV_ISA_EXT_ZBC,
> + RISCV_ISA_EXT_ZBKB,
> + RISCV_ISA_EXT_ZBKC,
> + RISCV_ISA_EXT_ZBKX,
> + RISCV_ISA_EXT_ZBS,
> + RISCV_ISA_EXT_ZKND,
> + RISCV_ISA_EXT_ZKNE,
> + RISCV_ISA_EXT_ZKNH,
> + RISCV_ISA_EXT_ZKR,
> + RISCV_ISA_EXT_ZKSED,
> + RISCV_ISA_EXT_ZKSH,
> + RISCV_ISA_EXT_ZKT,
> + RISCV_ISA_EXT_SSCOFPMF,
> RISCV_ISA_EXT_SVPBMT,
> RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX,
> };
> diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
> index 40c8776aec12..9d2bed2c1a37 100644
> --- a/arch/riscv/kernel/cpu.c
> +++ b/arch/riscv/kernel/cpu.c
> @@ -87,6 +87,20 @@ int riscv_of_parent_hartid(struct device_node *node)
> * extensions by an underscore.
> */
> static struct riscv_isa_ext_data isa_ext_arr[] = {
> + __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
> + __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
> + __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC),
> + __RISCV_ISA_EXT_DATA(zbkb, RISCV_ISA_EXT_ZBKB),
> + __RISCV_ISA_EXT_DATA(zbkc, RISCV_ISA_EXT_ZBKC),
> + __RISCV_ISA_EXT_DATA(zbkx, RISCV_ISA_EXT_ZBKX),
> + __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),
> + __RISCV_ISA_EXT_DATA(zknd, RISCV_ISA_EXT_ZKND),
> + __RISCV_ISA_EXT_DATA(zkne, RISCV_ISA_EXT_ZKNE),
> + __RISCV_ISA_EXT_DATA(zknh, RISCV_ISA_EXT_ZKNH),
> + __RISCV_ISA_EXT_DATA(zkr, RISCV_ISA_EXT_ZKR),
> + __RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED),
> + __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH),
> + __RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT),
> __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
> __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
> __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index dea3ea19deee..800a7aebced3 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -199,6 +199,39 @@ void __init riscv_fill_hwcap(void)
> } else {
> SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF);
> SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
> + SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA);
> + SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB);
> + SET_ISA_EXT_MAP("zbc", RISCV_ISA_EXT_ZBC);
> + SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS);
> + SET_ISA_EXT_MAP("zbkb", RISCV_ISA_EXT_ZBKB);
> + SET_ISA_EXT_MAP("zbkc", RISCV_ISA_EXT_ZBKC);
> + SET_ISA_EXT_MAP("zbks", RISCV_ISA_EXT_ZBKX);
> + SET_ISA_EXT_MAP("zknd", RISCV_ISA_EXT_ZKND);
> + SET_ISA_EXT_MAP("zkne", RISCV_ISA_EXT_ZKNE);
> + SET_ISA_EXT_MAP("zknh", RISCV_ISA_EXT_ZKNH);
> + SET_ISA_EXT_MAP("zksed", RISCV_ISA_EXT_ZKSED);
> + SET_ISA_EXT_MAP("zksh", RISCV_ISA_EXT_ZKSH);
> + SET_ISA_EXT_MAP("zkr", RISCV_ISA_EXT_ZKR);
> + SET_ISA_EXT_MAP("zkt", RISCV_ISA_EXT_ZKT);
> + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZBKB);
> + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZBKC);
> + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZBKX);
> + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZKND);
> + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZKNE);
> + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZKNH);
> + SET_ISA_EXT_MAP("zks", RISCV_ISA_EXT_ZBKB);
> + SET_ISA_EXT_MAP("zks", RISCV_ISA_EXT_ZBKC);
> + SET_ISA_EXT_MAP("zks", RISCV_ISA_EXT_ZBKX);
> + SET_ISA_EXT_MAP("zks", RISCV_ISA_EXT_ZKSED);
> + SET_ISA_EXT_MAP("zks", RISCV_ISA_EXT_ZKSH);
> + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZBKB);
> + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZBKC);
> + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZBKX);
> + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZKND);
> + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZKNE);
> + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZKNH);
> + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZKR);
> + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZKT);
> }
> #undef SET_ISA_EXT_MAP
> }
> --
> 2.35.1
>
>
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