Re: [PATCH v13 3/4] arm64: dts: qcom: sc7280: add lpass lpi pin controller node
From: Srinivasa Rao Mandadapu
Date: Thu May 05 2022 - 10:15:43 EST
On 5/5/2022 3:30 AM, Matthias Kaehlcke wrote:
Thanks for your time Matthias!!!
On Wed, May 04, 2022 at 04:46:26PM +0530, Srinivasa Rao Mandadapu wrote:
Add LPASS LPI pinctrl node required for Audio functionality on sc7280
based platforms.
Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@xxxxxxxxxxx>
Co-developed-by: Venkata Prasad Potturu <quic_potturu@xxxxxxxxxxx>
Signed-off-by: Venkata Prasad Potturu <quic_potturu@xxxxxxxxxxx>
Reviewed-by: Stephen Boyd <swboyd@xxxxxxxxxxxx>
Reviewed-by: Matthias Kaehlcke <mka@xxxxxxxxxxxx>
Please remove my tag for now, the patch changed quite a bit since the
last version.
Okay. Will remove it.
---
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 64 ++++++++++++++++++++++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 91 ++++++++++++++++++++++++++++++++
2 files changed, 155 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index 754da58..fb0e313 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -367,6 +367,70 @@
bias-disable;
};
+&lpass_dmic01_clk {
+ drive-strength = <8>;
+ bias-disable;
+};
+
+&lpass_dmic01_data {
+ bias-pull-down;
+};
+
+&lpass_dmic01_clk_sleep {
+ drive-strength = <2>;
+};
Should be after 'lpass_dmic01_clk', not only because of alphanumerical sorting
order, but also because the two belong together.
Okay. Will sort accordingly.
+
+&lpass_dmic23_clk {
+ drive-strength = <8>;
+ bias-disable;
+};
+
+&lpass_dmic23_data {
+ bias-pull-down;
+};
+
+&lpass_dmic23_clk_sleep {
+ drive-strength = <2>;
+};
ditto
Okay.
+
+&lpass_rx_swr_clk {
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+};
+
+&lpass_rx_swr_data {
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+};
+
+&lpass_rx_swr_clk_sleep {
+ drive-strength = <2>;
The drive strength is the same as for 'lpass_rx_swr_clk', so I think you
could omit it?
Okay. will remove it and re post.
+ bias-pull-down;
+};
fix sorting order
Okay. Will sort accordingly.
+
+&lpass_rx_swr_data_sleep {
+ drive-strength = <2>;
drive strength not needed?
Okay.
+ bias-pull-down;
+};
+
+&lpass_tx_swr_clk {
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+};
+
+&lpass_tx_swr_data {
+ slew-rate = <1>;
+ bias-bus-hold;
+};
+
+&lpass_tx_swr_clk_sleep {
+ drive-strength = <2>;
drive strength not needed?
Okay.
+ bias-pull-down;
+};
fix sorting order
Okay. Will sort accordingly.
+
&mi2s1_data0 {
drive-strength = <6>;
bias-disable;
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index c5b6b46..c961ca1 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2224,6 +2224,97 @@
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ lpass_tlmm: pinctrl@33c0000 {
+ compatible = "qcom,sc7280-lpass-lpi-pinctrl";
+ reg = <0 0x033c0000 0x0 0x20000>,
+ <0 0x03550000 0x0 0x10000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&lpass_tlmm 0 0 15>;
+
+ #clock-cells = <1>;
+
+ lpass_dmic01_clk: dmic01-clk {
+ pins = "gpio6";
+ function = "dmic1_clk";
+ };
+
+ lpass_dmic01_data: dmic01-data {
+ pins = "gpio7";
+ function = "dmic1_data";
+ };
+
+ lpass_dmic01_clk_sleep: dmic01-clk-sleep {
+ pins = "gpio6";
+ function = "dmic1_clk";
+ };
fix sorting order
Okay. Will sort accordingly.
+
+ lpass_dmic01_data_sleep: dmic01-data-sleep {
+ pins = "gpio7";
+ function = "dmic1_data";
+ };
+
+ lpass_dmic23_clk: dmic23-clk {
+ pins = "gpio8";
+ function = "dmic2_clk";
+ };
+
+ lpass_dmic23_data: dmic23-data {
+ pins = "gpio9";
+ function = "dmic2_data";
+ };
+
+ lpass_dmic23_clk_sleep: dmic23-clk-sleep {
+ pins = "gpio8";
+ function = "dmic2_clk";
+ };
fix sorting order
Okay. Will sort accordingly.
+
+ lpass_dmic23_data_sleep: dmic23-data-sleep {
+ pins = "gpio9";
+ function = "dmic2_data";
+ };
+
+ lpass_rx_swr_clk: rx-swr-clk {
+ pins = "gpio3";
+ function = "swr_rx_clk";
+ };
+
+ lpass_rx_swr_data: rx-swr-data {
+ pins = "gpio4", "gpio5";
+ function = "swr_rx_data";
+ };
+
+ lpass_rx_swr_clk_sleep: rx-swr-clk-sleep {
+ pins = "gpio3";
+ function = "swr_rx_clk";
+ };
fix sorting order
Okay. Will sort accordingly.
+
+ lpass_rx_swr_data_sleep: rx-swr-data-sleep {
+ pins = "gpio4", "gpio5";
+ function = "swr_rx_data";
+ };
+
+ lpass_tx_swr_clk: tx-swr-clk {
+ pins = "gpio0";
+ function = "swr_tx_clk";
+ };
+
+ lpass_tx_swr_data: tx-swr-data {
+ pins = "gpio1", "gpio2", "gpio14";
+ function = "swr_tx_data";
+ };
+
+ lpass_tx_swr_clk_sleep: tx-swr-clk-sleep {
+ pins = "gpio0";
+ function = "swr_tx_clk";
+ };
fix sorting order
Okay. Will sort accordingly.
+
+ lpass_tx_swr_data_sleep: tx-swr-data-sleep {
+ pins = "gpio1", "gpio2", "gpio14";
+ function = "swr_tx_data";
+ };
+ };
+
gpu: gpu@3d00000 {
compatible = "qcom,adreno-635.0", "qcom,adreno";
reg = <0 0x03d00000 0 0x40000>,
--
2.7.4