Re: [PATCH v2 4/4] iommu/vt-d: Remove hard coding PGSNP bit in PASID entries

[Baolu Lu]

On 2022/5/5 16:46, Tian, Kevin wrote:
> > From: Lu Baolu <baolu.lu@xxxxxxxxxxxxxxx>
> > Sent: Thursday, May 5, 2022 9:07 AM
> >
> > As enforce_cache_coherency has been introduced into the
> > iommu_domain_ops,
> > the kernel component which owns the iommu domain is able to opt-in its
> > requirement for force snooping support. The iommu driver has no need to
> > hard code the page snoop control bit in the PASID table entries anymore.
> >
> > Signed-off-by: Lu Baolu <baolu.lu@xxxxxxxxxxxxxxx>
>
> Reviewed-by: Kevin Tian <kevin.tian@xxxxxxxxx>, with one nit:
>
> > ---
> >   drivers/iommu/intel/pasid.c | 3 ---
> >   1 file changed, 3 deletions(-)
> >
> > diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c
> > index 41a0e3b02c79..0abfa7fc7fb0 100644
> > --- a/drivers/iommu/intel/pasid.c
> > +++ b/drivers/iommu/intel/pasid.c
> > @@ -710,9 +710,6 @@ int intel_pasid_setup_second_level(struct
> > intel_iommu *iommu,
> >   	pasid_set_fault_enable(pte);
> >   	pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap));
>
> Probably in a separate patch but above should really be renamed
> to pasid_set_page_walk_snoop().

Yeah! Need a cleanup here. Above name is confusing.

> > -	if (domain->domain.type == IOMMU_DOMAIN_UNMANAGED)
> > -		pasid_set_pgsnp(pte);
> > -
> >   	/*
> >   	 * Since it is a second level only translation setup, we should
> >   	 * set SRE bit as well (addresses are expected to be GPAs).
> > --
> > 2.25.1

Best regards,
baolu