[PATCH V4 0/5] riscv: Optimize atomic implementation

From: guoren
Date: Wed May 04 2022 - 23:55:48 EST


From: Guo Ren <guoren@xxxxxxxxxxxxxxxxx>

Here are some optimizations for riscv atomic implementation, the first
three patches are normal cleanup and custom implementation without
relating to atomic semantics.

The 4th is the same as arm64 LSE with using embedded .aq/.rl
annotation.

The 5th is good for riscv implementation with reducing a full-barrier
cost.

Changes in V4:
- Coding convention & optimize the comments
- Re-order the patchset

Changes in V3:
- Fixup usage of lr.rl & sc.aq with violation of ISA
- Add Optimize dec_if_positive functions
- Add conditional atomic operations' optimization

Changes in V2:
- Fixup LR/SC memory barrier semantic problems which pointed by
Rutland
- Combine patches into one patchset series
- Separate AMO optimization & LRSC optimization for convenience
patch review

Guo Ren (5):
riscv: atomic: Cleanup unnecessary definition
riscv: atomic: Optimize acquire and release for AMO operations
riscv: atomic: Optimize memory barrier semantics of LRSC-pairs
riscv: atomic: Optimize dec_if_positive functions
riscv: atomic: Add conditional atomic operations' optimization

Guo Ren (5):
riscv: atomic: Cleanup unnecessary definition
riscv: atomic: Optimize dec_if_positive functions
riscv: atomic: Add custom conditional atomic operation implementation
riscv: atomic: Optimize atomic_ops & xchg with .aq/rl annotation
riscv: atomic: Optimize LRSC-pairs atomic ops with .aqrl annotation

arch/riscv/include/asm/atomic.h | 174 +++++++++++++++++++++++++++----
arch/riscv/include/asm/cmpxchg.h | 30 ++----
2 files changed, 162 insertions(+), 42 deletions(-)

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2.25.1