Re: [PATCH v4 5/7] RISC-V: Move to generic spinlocks

[Guo Ren]

Reviewed-by: Guo Ren <guoren@xxxxxxxxxx>

On Wed, May 4, 2022 at 8:02 PM Heiko Stübner <heiko@xxxxxxxxx> wrote:
>
> Am Samstag, 30. April 2022, 17:36:24 CEST schrieb Palmer Dabbelt:
> > From: Palmer Dabbelt <palmer@xxxxxxxxxxxx>
> >
> > Our existing spinlocks aren't fair and replacing them has been on the
> > TODO list for a long time.  This moves to the recently-introduced ticket
> > spinlocks, which are simple enough that they are likely to be correct
> > and fast on the vast majority of extant implementations.
> >
> > This introduces a horrible hack that allows us to split out the spinlock
> > conversion from the rwlock conversion.  We have to do the spinlocks
> > first because qrwlock needs fair spinlocks, but we don't want to pollute
> > the asm-generic code to support the generic spinlocks without qrwlocks.
> > Thus we pollute the RISC-V code, but just until the next commit as it's
> > all going away.
> >
> > Signed-off-by: Palmer Dabbelt <palmer@xxxxxxxxxxxx>
>
> on riscv64+riscv32 qemu, beaglev and d1-nezha
>
> Tested-by: Heiko Stuebner <heiko@xxxxxxxxx>
>
>


-- 
Best Regards
 Guo Ren

ML: https://lore.kernel.org/linux-csky/