[irqchip: irq/irqchip-next] irqchip/gic-v3: Exposes bit values for GICR_CTLR.{IR, CES}
From: irqchip-bot for Marc Zyngier
Date: Wed May 04 2022 - 11:16:09 EST
The following commit has been merged into the irq/irqchip-next branch of irqchip:
Commit-ID: 34453c2e9f799d02f5f379519495208bbd96a935
Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/34453c2e9f799d02f5f379519495208bbd96a935
Author: Marc Zyngier <maz@xxxxxxxxxx>
AuthorDate: Tue, 05 Apr 2022 19:23:24 +01:00
Committer: Marc Zyngier <maz@xxxxxxxxxx>
CommitterDate: Wed, 04 May 2022 14:09:52 +01:00
irqchip/gic-v3: Exposes bit values for GICR_CTLR.{IR, CES}
As we're about to expose GICR_CTLR.{IR,CES} to guests, populate
the include file with the architectural values.
Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx>
Reviewed-by: Oliver Upton <oupton@xxxxxxxxxx>
Link: https://lore.kernel.org/r/20220405182327.205520-2-maz@xxxxxxxxxx
---
include/linux/irqchip/arm-gic-v3.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index 12d91f0..7286913 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -127,6 +127,8 @@
#define GICR_PIDR2 GICD_PIDR2
#define GICR_CTLR_ENABLE_LPIS (1UL << 0)
+#define GICR_CTLR_CES (1UL << 1)
+#define GICR_CTLR_IR (1UL << 2)
#define GICR_CTLR_RWP (1UL << 3)
#define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff)