Re: [PATCH 6/7] perf/x86/amd/core: Add PerfMonV2 overflow handling
From: Sandipan Das
Date: Tue Mar 22 2022 - 04:38:25 EST
On 3/22/2022 12:36 PM, Like Xu wrote:
> On 17/3/2022 2:28 pm, Sandipan Das wrote:
>> + val = x86_perf_event_update(event);
>
> The variable 'val' set but not used.
>
>> + mask = BIT_ULL(idx);
>> +
>> + if (!(status & mask))
>
> Needed here ?
>
If you are referring to this previous usage of 'val' within
x86_pmu_handle_irq():
if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
then, no. Instead of looking at bit 47 of the raw counter value,
one can look at the overflow bits of the global status register
to determine if a counter overflow has occurred.
Will remove 'val' as you suggested since it is no longer needed
for any decision making.