Re: [PATCH v2 5/7] kvm/riscv: rework guest entry logic

[Paolo Bonzini]

On 1/19/22 11:58, Mark Rutland wrote:
> +		 * There's no barrier which ensures that pending interrupts are
> +		 * recognised, so we just hope that the CPU takes any pending
> +		 * interrupts between the enable and disable.
>   		 */
>   		local_irq_enable();
> +		local_irq_disable();
>   

This should be the required architectural behavior: "a CSR access is 
performed after the execution of any prior instructions in program order 
whose behavior modifies or is modified by the CSR state and before the 
execution of any subsequent instructions in program order whose behavior 
modifies or is modified by the CSR state" (Zicsr spec, paragraph "CSR 
Access Ordering", available at 
https://www.five-embeddev.com/riscv-isa-manual/latest/csr.html#csrinsts).

Paolo