Re: [PATCH v8] libperf: Add arm64 support to perf_mmap__read_self()

[Rob Herring]

On Fri, Jan 14, 2022 at 8:19 AM Ian Rogers <irogers@xxxxxxxxxx> wrote:
>
> On Tue, Dec 14, 2021, 1:56 PM Rob Herring <robh@xxxxxxxxxx> wrote:
>>
>> Add the arm64 variants for read_perf_counter() and read_timestamp().
>> Unfortunately the counter number is encoded into the instruction, so the
>> code is a bit verbose to enumerate all possible counters.
>>
>> Signed-off-by: Rob Herring <robh@xxxxxxxxxx>
>> ---
>> v8:
>>  - Set attr.config1 to request user access on arm64
>> v7:
>>  - Move enabling of libperf user read test for arm64 to this patch
>> ---
>>  tools/lib/perf/mmap.c             | 98 +++++++++++++++++++++++++++++++
>>  tools/lib/perf/tests/test-evsel.c |  5 +-
>>  2 files changed, 102 insertions(+), 1 deletion(-)
>>
>> diff --git a/tools/lib/perf/mmap.c b/tools/lib/perf/mmap.c
>> index c89dfa5f67b3..7ee3eb9f5e27 100644
>> --- a/tools/lib/perf/mmap.c
>> +++ b/tools/lib/perf/mmap.c
>> @@ -13,6 +13,7 @@
>>  #include <internal/lib.h>
>>  #include <linux/kernel.h>
>>  #include <linux/math64.h>
>> +#include <linux/stringify.h>
>>  #include "internal.h"
>>
>>  void perf_mmap__init(struct perf_mmap *map, struct perf_mmap *prev,
>> @@ -294,6 +295,103 @@ static u64 read_timestamp(void)
>>
>>         return low | ((u64)high) << 32;
>>  }
>> +#elif defined(__aarch64__)
>> +#define read_sysreg(r) ({                                              \
>> +       u64 __val;                                                      \
>> +       asm volatile("mrs %0, " __stringify(r) : "=r" (__val));         \
>> +       __val;                                                          \
>> +})
>> +
>> +static u64 read_pmccntr(void)
>> +{
>> +       return read_sysreg(pmccntr_el0);
>> +}
>> +
>> +#define PMEVCNTR_READ(idx)                                     \
>> +       static u64 read_pmevcntr_##idx(void) {                  \
>> +               return read_sysreg(pmevcntr##idx##_el0);        \
>> +       }
>> +
>> +PMEVCNTR_READ(0);
>> +PMEVCNTR_READ(1);
>> +PMEVCNTR_READ(2);
>> +PMEVCNTR_READ(3);
>> +PMEVCNTR_READ(4);
>> +PMEVCNTR_READ(5);
>> +PMEVCNTR_READ(6);
>> +PMEVCNTR_READ(7);
>> +PMEVCNTR_READ(8);
>> +PMEVCNTR_READ(9);
>> +PMEVCNTR_READ(10);
>> +PMEVCNTR_READ(11);
>> +PMEVCNTR_READ(12);
>> +PMEVCNTR_READ(13);
>> +PMEVCNTR_READ(14);
>> +PMEVCNTR_READ(15);
>> +PMEVCNTR_READ(16);
>> +PMEVCNTR_READ(17);
>> +PMEVCNTR_READ(18);
>> +PMEVCNTR_READ(19);
>> +PMEVCNTR_READ(20);
>> +PMEVCNTR_READ(21);
>> +PMEVCNTR_READ(22);
>> +PMEVCNTR_READ(23);
>> +PMEVCNTR_READ(24);
>> +PMEVCNTR_READ(25);
>> +PMEVCNTR_READ(26);
>> +PMEVCNTR_READ(27);
>> +PMEVCNTR_READ(28);
>> +PMEVCNTR_READ(29);
>> +PMEVCNTR_READ(30);
>
>
> Nit: It looks strange that 31 is not here, ie 31 counters rather than 32.

>From the Arm ARM:
D13.4.8
PMEVCNTR<n>_EL0, Performance Monitors Event Count Registers, n = 0 - 30

The 32nd counter is the cycle counter which is special and accessed in
a different register.

Rob