On Thu, Dec 16, 2021 at 3:14 PM Jiaxun Yang <jiaxun.yang@xxxxxxxxxxx> wrote:
在 2021/12/16 13:50, Arnd Bergmann 写道:Are PIO accesses common enough that the TLB entry makes a difference?
On Thu, Dec 16, 2021 at 2:07 PM Jiaxun Yang <jiaxun.yang@xxxxxxxxxxx> wrote:Yes, the Arm way was my previous approach when introducing PCI IO map
在2021年12月16日十二月 上午11:44,Xi Ruoyao写道:I think that would add a lot of complexity that isn't needed here. Not
Another way could be keeping a linked list about PIO->PHYS mapping instead of using the single io_port_base variable.
sure if all MIPS CPUs
can do it, but the approach used on Arm is what fits in best with the
PCI drivers, these
reserve a virtual address range for the ports, and ioremap the
physical addresses into
the PIO range according to the mapping.
for Loongson.
It got refactored by this patch as TLB entries are expensive on MIPS,
also the size of IO range doesn't always fits a page.
I would imagine that on most systems with a PCI bus, there is not even
a single device that exposes an I/O resource, and even on those devices that
do, the kernel drivers tend to pick MMIO whenever both are available.
- Jiaxun
Arnd