[Patch Resend v1 2/8] dt-bindings: arm: tegra: Add NVIDIA Tegra194 CBB1.0 binding

[Sumit Gupta]

Add device-tree binding documentation to represent the error handling
driver for Control Backbone (CBB) version 1.0 used in Tegra194 SOC.
The driver prints debug information about failed transactions due to
illegal register accesses on receiving interrupt from CBB.

Signed-off-by: Sumit Gupta <sumitg@xxxxxxxxxx>
---
 .../arm/tegra/nvidia,tegra194-cbb.yaml        | 121 ++++++++++++++++++
 1 file changed, 121 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-cbb.yaml

diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-cbb.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-cbb.yaml
new file mode 100644
index 000000000000..a9b5a1eab909
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-cbb.yaml
@@ -0,0 +1,121 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+
+$id: "http://devicetree.org/schemas/arm/tegra/tegra19_cbb.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: NVIDIA Tegra194 CBB1.0 Error handling driver device tree bindings
+
+maintainers:
+  - Sumit Gupta <sumitg@xxxxxxxxxx>
+
+description: |+
+  Control Backbone (CBB) comprises of the physical path from an
+  initiator to a target's register configuration space.
+  CBB1.0 has multiple hierarchical sub-NOC's (Network-on-Chip) and
+  connects various initiators and targets using different bridges
+  like AXIP2P, AXI2APB.
+  This driver handles errors due to illegal register accesses reported
+  by the NOC's inside CBB. NOC's reporting errors are cluster NOC's
+  "AON-NOC, SCE-NOC, RCE-NOC, BPMP-NOC, CV-NOC" and "CBB Central NOC"
+  which is the main NOC.
+
+  By default, the access issuing initiator is informed about the error
+  using SError or Data Abort exception unless the ERD (Error Response
+  Disable) is enabled/set for that initiator. If the ERD is enabled,
+  then SError or Data Abort is masked and the error is reported with
+  interrupt.
+
+  - For CCPLEX (CPU Complex) initiator, the driver sets ERD bit. So,
+    the errors due to illegal accesses from CCPLEX are reported by
+    interrupts. If ERD is not set, then error is reported by SError.
+  - For other initiators, the ERD is disabled. So, the access issuing
+    initiator is informed about the illegal access by Data Abort
+    exception. In addition, an interrupt is also generated to CCPLEX.
+    These initiators include all engines using Cortex-R5 (which is
+    ARMv7 CPU cluster) and engines like TSEC (Security co-processor),
+    NVDEC (NVIDIA Video Decoder engine) etc which can initiate
+    transactions.
+
+  The driver prints relevant debug information like Error Code, Error
+  Description, Master, Address, AXI ID, Cache, Protection, Security
+  Group etc on receiving error notification.
+
+properties:
+  $nodename:
+    pattern: "^[a-f]+-noc@[0-9a-f]+$"
+
+  compatible:
+    enum:
+      - nvidia,tegra194-cbb-noc
+      - nvidia,tegra194-aon-noc
+      - nvidia,tegra194-bpmp-noc
+      - nvidia,tegra194-rce-noc
+      - nvidia,tegra194-sce-noc
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 2
+    minItems: 2
+    items:
+      - description: non-secure interrupt
+      - description: secure interrupt
+    description:
+      CCPLEX receives secure or nonsecure interrupt depending on error type.
+      Secure interrupt is received for SEC(firewall) & SLV errors and
+      Non-secure interrupt is received for TMO & DEC errors.
+
+  nvidia,axi2apb:
+    $ref: '/schemas/types.yaml#/definitions/phandle'
+    description:
+      Specifies the node having all axi2apb bridges which need to be checked
+      for any error logged in their status register.
+
+  nvidia,apbmisc:
+    $ref: '/schemas/types.yaml#/definitions/phandle'
+    description:
+      Specifies the apbmisc node which need to be used for reading ERD register.
+
+additionalProperties: true
+
+examples:
+  - |
+    cbb-noc@2300000 {
+        compatible = "nvidia,tegra194-cbb-noc";
+        reg = <0x02300000 0x1000>;
+        interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+        nvidia,axi2apb = <&axi2apb>;
+        nvidia,apbmisc = <&apbmisc>;
+        status = "okay";
+    };
+
+properties:
+  $nodename:
+    const: axi2apb@2390000
+    description: AXI2APB bridge
+
+  compatible:
+    enum:
+      - nvidia,tegra194-axi2apb-bridge
+
+  reg:
+    maxItems: 6
+    description: Physical base address and length of registers for all bridges
+
+examples:
+  - |
+    axi2apb: axi2apb@2390000 {
+        compatible = "nvidia,tegra194-axi2apb-bridge";
+        reg = <0x02390000 0x1000>,
+            <0x023A0000 0x1000>,
+            <0x023B0000 0x1000>,
+            <0x023C0000 0x1000>,
+            <0x023D0000 0x1000>,
+            <0x023E0000 0x1000>;
+        status = "okay";
+    };
+...
-- 
2.17.1