[PATCH v3] PCI: Add ACS quirk for NXP LX2XX0 and LX2XX2 platforms

[Wasim Khan]

From: Wasim Khan <wasim.khan@xxxxxxx>

Root Ports in NXP LX2XX0 and LX2XX2 where each Root Port
is a Root Complex with unique segment numbers do provide
isolation features to disable peer transactions and
validate bus numbers in requests, but do not provide an
actual PCIe ACS capability.

Add ACS quirk for NXP LX2XX0 A/C/E/N and LX2XX2 A/C/E/N
platforms

LX2XX0A : without security features + CAN-FD
	  LX2160A (0x8d81) - 16 cores
	  LX2120A (0x8da1) - 12 cores
	  LX2080A (0x8d83) - 8  cores

LX2XX0C : security features + CAN-FD
	  LX2160C (0x8d80) - 16 cores
	  LX2120C (0x8da0) - 12 cores
	  LX2080C (0x8d82) - 8  cores

LX2XX0E : security features + CAN
	  LX2160E (0x8d90) - 16 cores
	  LX2120E (0x8db0) - 12 cores
	  LX2080E (0x8d92) - 8  cores

LX2XX0N : without security features + CAN
	  LX2160N (0x8d91) - 16 cores
	  LX2120N (0x8db1) - 12 cores
	  LX2080N (0x8d93) - 8  cores

LX2XX2A : without security features + CAN-FD
	  LX2162A (0x8d89) - 16 cores
	  LX2122A (0x8da9) - 12 cores
	  LX2082A (0x8d8b) - 8  cores

LX2XX2C : security features + CAN-FD
	  LX2162C (0x8d88) - 16 cores
	  LX2122C (0x8da8) - 12 cores
	  LX2082C (0x8d8a) - 8  cores

LX2XX2E : security features + CAN
	  LX2162E (0x8d98) - 16 cores
	  LX2122E (0x8db8) - 12 cores
	  LX2082E (0x8d9a) - 8  cores

LX2XX2N : without security features + CAN
	  LX2162N (0x8d99) - 16 cores
	  LX2122N (0x8db9) - 12 cores
	  LX2082N (0x8d9b) - 8  cores

Signed-off-by: Wasim Khan <wasim.khan@xxxxxxx>
---
Changes in v3:
- Updated PCIe ID for LX2XX0 and LX2XX2 A/C/E/N
  platforms and arranged then in order
- Updated commit description and included
  device to ID mapping
 
 drivers/pci/quirks.c | 31 ++++++++++++++++++++++++++++++-
 1 file changed, 30 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 24343a76c034..d445d2944592 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -4784,9 +4784,38 @@ static const struct pci_dev_acs_enabled {
 	{ PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs },
 	{ PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs },
 	/* NXP root ports */
+	/* LX2XX0A */
+	{ PCI_VENDOR_ID_NXP, 0x8d81, pci_quirk_nxp_rp_acs },
+	{ PCI_VENDOR_ID_NXP, 0x8da1, pci_quirk_nxp_rp_acs },
+	{ PCI_VENDOR_ID_NXP, 0x8d83, pci_quirk_nxp_rp_acs },
+	/* LX2XX0C */
 	{ PCI_VENDOR_ID_NXP, 0x8d80, pci_quirk_nxp_rp_acs },
-	{ PCI_VENDOR_ID_NXP, 0x8d88, pci_quirk_nxp_rp_acs },
+	{ PCI_VENDOR_ID_NXP, 0x8da0, pci_quirk_nxp_rp_acs },
+	{ PCI_VENDOR_ID_NXP, 0x8d82, pci_quirk_nxp_rp_acs },
+	/* LX2XX0E */
+	{ PCI_VENDOR_ID_NXP, 0x8d90, pci_quirk_nxp_rp_acs },
+	{ PCI_VENDOR_ID_NXP, 0x8db0, pci_quirk_nxp_rp_acs },
+	{ PCI_VENDOR_ID_NXP, 0x8d92, pci_quirk_nxp_rp_acs },
+	/* LX2XX0N */
+	{ PCI_VENDOR_ID_NXP, 0x8d91, pci_quirk_nxp_rp_acs },
+	{ PCI_VENDOR_ID_NXP, 0x8db1, pci_quirk_nxp_rp_acs },
+	{ PCI_VENDOR_ID_NXP, 0x8d93, pci_quirk_nxp_rp_acs },
+	/* LX2XX2A */
 	{ PCI_VENDOR_ID_NXP, 0x8d89, pci_quirk_nxp_rp_acs },
+	{ PCI_VENDOR_ID_NXP, 0x8da9, pci_quirk_nxp_rp_acs },
+	{ PCI_VENDOR_ID_NXP, 0x8d8b, pci_quirk_nxp_rp_acs },
+	/* LX2XX2C */
+	{ PCI_VENDOR_ID_NXP, 0x8d88, pci_quirk_nxp_rp_acs },
+	{ PCI_VENDOR_ID_NXP, 0x8da8, pci_quirk_nxp_rp_acs },
+	{ PCI_VENDOR_ID_NXP, 0x8d8a, pci_quirk_nxp_rp_acs },
+	/* LX2XX2E */
+	{ PCI_VENDOR_ID_NXP, 0x8d98, pci_quirk_nxp_rp_acs },
+	{ PCI_VENDOR_ID_NXP, 0x8db8, pci_quirk_nxp_rp_acs },
+	{ PCI_VENDOR_ID_NXP, 0x8d9a, pci_quirk_nxp_rp_acs },
+	/* LX2XX2N */
+	{ PCI_VENDOR_ID_NXP, 0x8d99, pci_quirk_nxp_rp_acs },
+	{ PCI_VENDOR_ID_NXP, 0x8db9, pci_quirk_nxp_rp_acs },
+	{ PCI_VENDOR_ID_NXP, 0x8d9b, pci_quirk_nxp_rp_acs },
 	/* Zhaoxin Root/Downstream Ports */
 	{ PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs },
 	{ 0 }
-- 
2.25.1