Re: [PATCH 0/2] Fix double counting of S/W ECC engines' ECC stat

[Miquel Raynal]

Hi YouChing,

ycllin@xxxxxxxxxxx wrote on Thu, 13 May 2021 10:11:02 +0800:

> > "Miquel Raynal" <miquel.raynal@xxxxxxxxxxx>   
> <deleted>
> > 
> > Good catch!
> > 
> > However I don't think the current fix is valid because these engines
> > are meant to be used by the raw NAND core as well, I propose something
> > like the below, can you please tell me if it works as expected? (not
> > even build tested)
> > 
> > Thanks,
> > Miquèl
> > 
> >   
> <deleted>
> 
> Thanks for your work.
> 
> I tested the two patches(yours and mine) separately in our environment: 
> 1) MXIC NFC(&raw NAND),2) MXIC SPI host(&SPI-NAND) with S/W BCH engine. 
> Both patches are valid(using nandtest/nandbiterrs, values of ecc_stats are 
> normal).
> 
> This seems to be because the function(nand_ecc_sw_bch_finish_io_req() 
> in ecc-sw-bch.c) that would increase the ecc_stats counter is not used 
> in the raw NAND world. Am I misunderstanding or is it platform dependency?

I don't think it can be called a platform dependency, it's more like
legacy from the raw NAND world which makes the use of the generic ECC
framework hard and thus is limited to a given set of functions.

> BTW, I think your modification should be more in line with the design 
> spirit 
> of generic ECC engine framework.

Yes, ideally raw NAND should fully comply to this framework but this
would require a hundred days of work and dozens of available boards to
test. During the past 20 years people assumed NAND controller and ECC
engine were a single entity which makes the use of the generic ECC
framework hard to implemented in the raw NAND. So I decided not to put
all my energy there in order to first get this framework available to
SPI-NAND devices.

Thanks,
Miquèl