Re: [PATCH RESEND 1/2] perf/x86: Skip checking MSR for MSR 0x0

From: Sean Christopherson
Date: Wed Apr 21 2021 - 11:30:23 EST


On Wed, Apr 21, 2021, Like Xu wrote:
> The Architecture LBR does not have MSR_LBR_TOS (0x000001c9).
> When ARCH_LBR we don't set lbr_tos, the failure from the
> check_msr() against MSR 0x000 will make x86_pmu.lbr_nr = 0,
> thereby preventing the initialization of the guest LBR.
>
> Fixes: 47125db27e47 ("perf/x86/intel/lbr: Support Architectural LBR")
> Signed-off-by: Like Xu <like.xu@xxxxxxxxxxxxxxx>
> Reviewed-by: Kan Liang <kan.liang@xxxxxxxxxxxxxxx>
> ---
> arch/x86/events/intel/core.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index 5272f349dca2..5036496caa60 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -4751,10 +4751,10 @@ static bool check_msr(unsigned long msr, u64 mask)
> u64 val_old, val_new, val_tmp;
>
> /*
> - * Disable the check for real HW, so we don't
> + * Disable the check for real HW or non-sense msr, so we don't

I think this should be "undefined MSR" or something along those lines. MSR 0x0
is a "real" MSR, on Intel CPUs it's an alias for IA32_MC0_ADDR; at least it's
supposed to be, most/all Intel CPUs incorrectly alias it to IA32_MC0_CTL.

Anyways, my point is that if your definition of "nonsense" is any MSR that is
not a valid perf MSR, then this check is woefully incompletely. If your
definition is a nonsensical value, then this comment is simply wrong.

What you're really looking for is precisely the case where the MSR was zero
initialized and never defined.

> * mess with potentionaly enabled registers:
> */
> - if (!boot_cpu_has(X86_FEATURE_HYPERVISOR))
> + if (!boot_cpu_has(X86_FEATURE_HYPERVISOR) || !msr)
> return true;
>
> /*
> --
> 2.30.2
>