[kbuild] Re: [PATCH net-next v2 1/2] of: net: pass the dst buffer to of_get_mac_address()

From: Dan Carpenter
Date: Fri Apr 09 2021 - 05:07:32 EST

Next message:
Previous
Messages

Hi Michael,

I love your patch! Perhaps
[auto build test WARNING
url: If you fix the issue, Reported-by: kernel Reported-by: Dan Carpenter
smatch warnings:
drivers/net/ethernet/xilinx/x
vim +/PTR_ERR +2069
2be586205ca2b8 Srikanth Thokala 8a3b7a252dca9f Daniel Borkmann 8495659bf93c8e Srikanth Thokala 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 28ef9ebdb64c6f Robert Hancock 411b125c6ace1f Michael Walle
5fff0151b3244d Andre Przywara 8495659bf93c8e Srikanth Thokala 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 41de8d4cff21a2 Joe Perches 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 95219aa538e11d Srikanth Thokala 8a3b7a252dca9f Daniel Borkmann 95219aa538e11d Srikanth Thokala 8a3b7a252dca9f Daniel Borkmann 28e24c62ab3062 Eric Dumazet 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann d894be57ca92c8 Jarod Wilson d894be57ca92c8 Jarod Wilson d894be57ca92c8 Jarod Wilson d894be57ca92c8 Jarod Wilson 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 95219aa538e11d Srikanth Thokala 8a3b7a252dca9f Daniel Borkmann 8b09ca823ffb4e Robert Hancock 8b09ca823ffb4e Robert Hancock 57baf8cc70ea4c Robert Hancock b11bfb9a19f9d7 Robert Hancock b11bfb9a19f9d7 Robert Hancock b11bfb9a19f9d7 Robert Hancock b11bfb9a19f9d7 Robert Hancock b11bfb9a19f9d7 Robert Hancock b11bfb9a19f9d7 Robert Hancock b11bfb9a19f9d7 Robert Hancock b11bfb9a19f9d7 Robert Hancock b11bfb9a19f9d7 Robert Hancock 57baf8cc70ea4c Robert Hancock 57baf8cc70ea4c Robert Hancock b11bfb9a19f9d7 Robert Hancock 57baf8cc70ea4c Robert Hancock b11bfb9a19f9d7 Robert Hancock 57baf8cc70ea4c Robert Hancock 57baf8cc70ea4c Robert Hancock 57baf8cc70ea4c Robert Hancock b11bfb9a19f9d7 Robert Hancock b11bfb9a19f9d7 Robert Hancock b11bfb9a19f9d7 Robert Hancock b11bfb9a19f9d7 Robert Hancock b11bfb9a19f9d7 Robert Hancock b11bfb9a19f9d7 Robert Hancock b11bfb9a19f9d7 Robert Hancock b11bfb9a19f9d7 Robert Hancock b11bfb9a19f9d7 Robert Hancock b11bfb9a19f9d7 Robert Hancock b11bfb9a19f9d7 Robert Hancock b11bfb9a19f9d7 Robert Hancock 8a3b7a252dca9f Daniel Borkmann 46aa27df885321 Srikanth Thokala 46aa27df885321 Srikanth Thokala fcc028c106e575 Krzysztof fcc028c106e575 Krzysztof 59cd4f19267a0a Robert Hancock 8a3b7a252dca9f Daniel Borkmann 7fa0043d5c74c6 Robert Hancock 46aa27df885321 Srikanth Thokala 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 8495659bf93c8e Srikanth Thokala 8495659bf93c8e Srikanth Thokala 8495659bf93c8e Srikanth Thokala 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 8495659bf93c8e Srikanth Thokala 8495659bf93c8e Srikanth Thokala 8495659bf93c8e Srikanth Thokala 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann f080a8c35d8932 Srikanth Thokala f080a8c35d8932 Srikanth Thokala f080a8c35d8932 Srikanth Thokala f080a8c35d8932 Srikanth Thokala f080a8c35d8932 Srikanth Thokala 8495659bf93c8e Srikanth Thokala ee06b1728b9564 Alvaro G. M 6c8f06bb2e5147 Robert Hancock 6c8f06bb2e5147 Robert Hancock 6c8f06bb2e5147 Robert Hancock ee06b1728b9564 Alvaro G. M ee06b1728b9564 Alvaro G. M ee06b1728b9564 Alvaro G. M ee06b1728b9564 Alvaro G. M ee06b1728b9564 Alvaro G. M ee06b1728b9564 Alvaro G. M ee06b1728b9564 Alvaro G. M ee06b1728b9564 Alvaro G. M ee06b1728b9564 Alvaro G. M ee06b1728b9564 Alvaro G. M ee06b1728b9564 Alvaro G. M ee06b1728b9564 Alvaro G. M ee06b1728b9564 Alvaro G. M ee06b1728b9564 Alvaro G. M ee06b1728b9564 Alvaro G. M ee06b1728b9564 Alvaro G. M ee06b1728b9564 Alvaro G. M ee06b1728b9564 Alvaro G. M ee06b1728b9564 Alvaro G. M ee06b1728b9564 Alvaro G. M ee06b1728b9564 Alvaro G. M ee06b1728b9564 Alvaro G. M 59cd4f19267a0a Robert Hancock ee06b1728b9564 Alvaro G. M ee06b1728b9564 Alvaro G. M 0c65b2b90d13c1 Andrew Lunn 0c65b2b90d13c1 Andrew Lunn 59cd4f19267a0a Robert Hancock ee06b1728b9564 Alvaro G. M 6c8f06bb2e5147 Robert Hancock 6c8f06bb2e5147 Robert Hancock 6c8f06bb2e5147 Robert Hancock 6c8f06bb2e5147 Robert Hancock 59cd4f19267a0a Robert Hancock 6c8f06bb2e5147 Robert Hancock 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann 95219aa538e11d Srikanth Thokala 28ef9ebdb64c6f Robert Hancock 28ef9ebdb64c6f Robert Hancock 28ef9ebdb64c6f Robert Hancock 46aa27df885321 Srikanth Thokala 46aa27df885321 Srikanth Thokala 28ef9ebdb64c6f Robert Hancock 28ef9ebdb64c6f Robert Hancock fa3a419d2f674b Wen Yang 59cd4f19267a0a Robert Hancock 46aa27df885321 Srikanth Thokala 28ef9ebdb64c6f Robert Hancock 28ef9ebdb64c6f Robert Hancock 28ef9ebdb64c6f Robert Hancock 28ef9ebdb64c6f Robert Hancock 28ef9ebdb64c6f Robert Hancock d6349e3e14c7f7 Andre Przywara 28ef9ebdb64c6f Robert Hancock 28ef9ebdb64c6f Robert Hancock 28ef9ebdb64c6f Robert Hancock 28ef9ebdb64c6f Robert Hancock 28ef9ebdb64c6f Robert Hancock 28ef9ebdb64c6f Robert Hancock 28ef9ebdb64c6f Robert Hancock d6349e3e14c7f7 Andre Przywara 28ef9ebdb64c6f Robert Hancock fcc028c106e575 Krzysztof 46aa27df885321 Srikanth Thokala fcc028c106e575 Krzysztof 59cd4f19267a0a Robert Hancock 8a3b7a252dca9f Daniel Borkmann cb59c87dbc8be2 Michal Simek 95219aa538e11d Srikanth Thokala 8a3b7a252dca9f Daniel Borkmann 59cd4f19267a0a Robert Hancock 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann f735c40ed93cca Andre Przywara f735c40ed93cca Andre Przywara f735c40ed93cca Andre Przywara f735c40ed93cca Andre Przywara f735c40ed93cca Andre Przywara f735c40ed93cca Andre Przywara f735c40ed93cca Andre Przywara f735c40ed93cca Andre Przywara f735c40ed93cca Andre Przywara f735c40ed93cca Andre Przywara f735c40ed93cca Andre Przywara f735c40ed93cca Andre Przywara f735c40ed93cca Andre Przywara f735c40ed93cca Andre Przywara f735c40ed93cca Andre Przywara f735c40ed93cca Andre Przywara 5fff0151b3244d Andre Przywara f735c40ed93cca Andre Przywara f735c40ed93cca Andre Przywara f735c40ed93cca Andre Przywara f735c40ed93cca Andre Przywara f735c40ed93cca Andre Przywara f735c40ed93cca Andre Przywara f735c40ed93cca Andre Przywara 5fff0151b3244d Andre Przywara 5fff0151b3244d Andre Przywara 5fff0151b3244d Andre Przywara 59cd4f19267a0a Robert Hancock 5fff0151b3244d Andre Przywara 5fff0151b3244d Andre Przywara 522856cefaf09d Robert Hancock 522856cefaf09d Robert Hancock 522856cefaf09d Robert Hancock 522856cefaf09d Robert Hancock 8a3b7a252dca9f Daniel Borkmann 411b125c6ace1f Michael Walle 411b125c6ace1f Michael Walle 411b125c6ace1f Michael Walle 411b125c6ace1f Michael Walle d05a9ed5c3a773 Robert Hancock d05a9ed5c3a773 Robert Hancock mac_addr isn't an error pointer.

411b125c6ace1f Michael Walle 8a3b7a252dca9f Daniel Borkmann 8a3b7a252dca9f Daniel Borkmann
---
0-DAY CI Kernel Test Description: application/gzip Nobuhiro Iwamatsu: "[PATCH v3 1/2] dt-bindings: pwm: Add bindings for Toshiba Visconti PWM Controller" message: Alexandre Chartre: "Re: [PATCH 1/2] x86/traps: call cond_local_irq_disable before returning from exc_general_protection and math_error" sorted by: [ date ] [ thread ] [ subject ] [ author ] something to improve:
on net-next/master]
href="https://github.com/0day-ci/linux/commits/Michael-Walle/of-net-support-non-platform-devices-in-of_get_mac_address/20210406-234030">https://github.com/0day-ci/linux/commits/Michael-Walle/of-net-support-non-platform-devices-in-of_get_mac_address/20210406-234030
href="https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git">https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git cc0626c2aaed8e475efdd85fa374b497a7192e35
(attached as .config)
9.3.0-22) 9.3.0
kindly add following tag as appropriate
test robot <lkp@xxxxxxxxx>
<dan.carpenter@xxxxxxxxxx>
ilinx_axienet_main.c:2069 axienet_probe() warn: passing a valid pointer to 'PTR_ERR'
drivers/net/ethernet/xilinx/xilinx_axienet_main.c
2015-05-05 1832 static int axienet_probe(struct platform_device *pdev)
2012-01-19 1833 {
2015-05-05 1834 int ret;
2012-01-19 1835 struct device_node *np;
2012-01-19 1836 struct axienet_local *lp;
2012-01-19 1837 struct net_device *ndev;
2019-06-06 1838 struct resource *ethres;
2021-04-06 1839 u8 mac_addr[ETH_ALEN];
^^^^^^^^^^^^^^^^^^^^^^
2020-03-24 1840 int addr_width = 32;
2015-05-05 1841 u32 value;
2012-01-19 1842
2012-01-19 1843 ndev = alloc_etherdev(sizeof(*lp));
2012-01-29 1844 if (!ndev)
2012-01-19 1845 return -ENOMEM;
2012-01-19 1846
2015-05-05 1847 platform_set_drvdata(pdev, ndev);
2012-01-19 1848
2015-05-05 1849 SET_NETDEV_DEV(ndev, &pdev->dev);
2012-01-19 1850 ndev->flags &= ~IFF_MULTICAST; /* clear multicast */
2013-12-02 1851 ndev->features = NETIF_F_SG;
2012-01-19 1852 ndev->netdev_ops = &axienet_netdev_ops;
2012-01-19 1853 ndev->ethtool_ops = &axienet_ethtool_ops;
2012-01-19 1854
2016-10-20 1855 /* MTU range: 64 - 9000 */
2016-10-20 1856 ndev->min_mtu = 64;
2016-10-20 1857 ndev->max_mtu = XAE_JUMBO_MTU;
2016-10-20 1858
2012-01-19 1859 lp = netdev_priv(ndev);
2012-01-19 1860 lp->ndev = ndev;
2015-05-05 1861 lp->dev = &pdev->dev;
2012-01-19 1862 lp->options = XAE_OPTION_DEFAULTS;
2019-06-06 1863 lp->rx_bd_num = RX_BD_NUM_DEFAULT;
2019-06-06 1864 lp->tx_bd_num = TX_BD_NUM_DEFAULT;
2021-02-12 1865
2021-03-25 1866 lp->axi_clk = devm_clk_get_optional(&pdev->dev, "s_axi_lite_clk");
2021-03-25 1867 if (!lp->axi_clk) {
2021-03-25 1868 /* For backward compatibility, if named AXI clock is not present,
2021-03-25 1869 * treat the first clock specified as the AXI clock.
2021-03-25 1870 */
2021-03-25 1871 lp->axi_clk = devm_clk_get_optional(&pdev->dev, NULL);
2021-03-25 1872 }
2021-03-25 1873 if (IS_ERR(lp->axi_clk)) {
2021-03-25 1874 ret = PTR_ERR(lp->axi_clk);
2021-02-12 1875 goto free_netdev;
2021-02-12 1876 }
2021-03-25 1877 ret = clk_prepare_enable(lp->axi_clk);
2021-02-12 1878 if (ret) {
2021-03-25 1879 dev_err(&pdev->dev, "Unable to enable AXI clock: %d\n", ret);
2021-02-12 1880 goto free_netdev;
2021-02-12 1881 }
2021-02-12 1882
2021-03-25 1883 lp->misc_clks[0].id = "axis_clk";
2021-03-25 1884 lp->misc_clks[1].id = "ref_clk";
2021-03-25 1885 lp->misc_clks[2].id = "mgt_clk";
2021-03-25 1886
2021-03-25 1887 ret = devm_clk_bulk_get_optional(&pdev->dev, XAE_NUM_MISC_CLOCKS, lp->misc_clks);
2021-03-25 1888 if (ret)
2021-03-25 1889 goto cleanup_clk;
2021-03-25 1890
2021-03-25 1891 ret = clk_bulk_prepare_enable(XAE_NUM_MISC_CLOCKS, lp->misc_clks);
2021-03-25 1892 if (ret)
2021-03-25 1893 goto cleanup_clk;
2021-03-25 1894
2012-01-19 1895 /* Map device registers */
2015-05-05 1896 ethres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2015-05-05 1897 lp->regs = devm_ioremap_resource(&pdev->dev, ethres);
Kozlowski 2015-07-09 1898 if (IS_ERR(lp->regs)) {
Kozlowski 2015-07-09 1899 ret = PTR_ERR(lp->regs);
2021-03-11 1900 goto cleanup_clk;
2012-01-19 1901 }
2019-06-11 1902 lp->regs_start = ethres->start;
2015-05-05 1903
2012-01-19 1904 /* Setup checksum offload, but default to off if not specified */
2012-01-19 1905 lp->features = 0;
2012-01-19 1906
2015-05-05 1907 ret = of_property_read_u32(pdev->dev.of_node, "xlnx,txcsum", &value);
2015-05-05 1908 if (!ret) {
2015-05-05 1909 switch (value) {
2012-01-19 1910 case 1:
2012-01-19 1911 lp->csum_offload_on_tx_path =
2012-01-19 1912 XAE_FEATURE_PARTIAL_TX_CSUM;
2012-01-19 1913 lp->features |= XAE_FEATURE_PARTIAL_TX_CSUM;
2012-01-19 1914 /* Can checksum TCP/UDP over IPv4. */
2012-01-19 1915 ndev->features |= NETIF_F_IP_CSUM;
2012-01-19 1916 break;
2012-01-19 1917 case 2:
2012-01-19 1918 lp->csum_offload_on_tx_path =
2012-01-19 1919 XAE_FEATURE_FULL_TX_CSUM;
2012-01-19 1920 lp->features |= XAE_FEATURE_FULL_TX_CSUM;
2012-01-19 1921 /* Can checksum TCP/UDP over IPv4. */
2012-01-19 1922 ndev->features |= NETIF_F_IP_CSUM;
2012-01-19 1923 break;
2012-01-19 1924 default:
2012-01-19 1925 lp->csum_offload_on_tx_path = XAE_NO_CSUM_OFFLOAD;
2012-01-19 1926 }
2012-01-19 1927 }
2015-05-05 1928 ret = of_property_read_u32(pdev->dev.of_node, "xlnx,rxcsum", &value);
2015-05-05 1929 if (!ret) {
2015-05-05 1930 switch (value) {
2012-01-19 1931 case 1:
2012-01-19 1932 lp->csum_offload_on_rx_path =
2012-01-19 1933 XAE_FEATURE_PARTIAL_RX_CSUM;
2012-01-19 1934 lp->features |= XAE_FEATURE_PARTIAL_RX_CSUM;
2012-01-19 1935 break;
2012-01-19 1936 case 2:
2012-01-19 1937 lp->csum_offload_on_rx_path =
2012-01-19 1938 XAE_FEATURE_FULL_RX_CSUM;
2012-01-19 1939 lp->features |= XAE_FEATURE_FULL_RX_CSUM;
2012-01-19 1940 break;
2012-01-19 1941 default:
2012-01-19 1942 lp->csum_offload_on_rx_path = XAE_NO_CSUM_OFFLOAD;
2012-01-19 1943 }
2012-01-19 1944 }
2012-01-19 1945 /* For supporting jumbo frames, the Axi Ethernet hardware must have
2015-05-05 1946 * a larger Rx/Tx Memory. Typically, the size must be large so that
2015-05-05 1947 * we can enable jumbo option and start supporting jumbo frames.
2015-05-05 1948 * Here we check for memory allocated for Rx/Tx in the hardware from
2015-05-05 1949 * the device-tree and accordingly set flags.
2015-05-05 1950 */
2015-05-05 1951 of_property_read_u32(pdev->dev.of_node, "xlnx,rxmem", &lp->rxmem);
2017-07-17 1952
2021-02-12 1953 lp->switch_x_sgmii = of_property_read_bool(pdev->dev.of_node,
2021-02-12 1954 "xlnx,switch-x-sgmii");
2021-02-12 1955
2017-07-17 1956 /* Start with the proprietary, and broken phy_type */
2017-07-17 1957 ret = of_property_read_u32(pdev->dev.of_node, "xlnx,phy-type", &value);
2017-07-17 1958 if (!ret) {
2017-07-17 1959 netdev_warn(ndev, "Please upgrade your device tree binary blob to use phy-mode");
2017-07-17 1960 switch (value) {
2017-07-17 1961 case XAE_PHY_TYPE_MII:
2017-07-17 1962 lp->phy_mode = PHY_INTERFACE_MODE_MII;
2017-07-17 1963 break;
2017-07-17 1964 case XAE_PHY_TYPE_GMII:
2017-07-17 1965 lp->phy_mode = PHY_INTERFACE_MODE_GMII;
2017-07-17 1966 break;
2017-07-17 1967 case XAE_PHY_TYPE_RGMII_2_0:
2017-07-17 1968 lp->phy_mode = PHY_INTERFACE_MODE_RGMII_ID;
2017-07-17 1969 break;
2017-07-17 1970 case XAE_PHY_TYPE_SGMII:
2017-07-17 1971 lp->phy_mode = PHY_INTERFACE_MODE_SGMII;
2017-07-17 1972 break;
2017-07-17 1973 case XAE_PHY_TYPE_1000BASE_X:
2017-07-17 1974 lp->phy_mode = PHY_INTERFACE_MODE_1000BASEX;
2017-07-17 1975 break;
2017-07-17 1976 default:
2017-07-17 1977 ret = -EINVAL;
2021-03-11 1978 goto cleanup_clk;
2017-07-17 1979 }
2017-07-17 1980 } else {
2019-11-04 1981 ret = of_get_phy_mode(pdev->dev.of_node, &lp->phy_mode);
2019-11-04 1982 if (ret)
2021-03-11 1983 goto cleanup_clk;
2017-07-17 1984 }
2021-02-12 1985 if (lp->switch_x_sgmii && lp->phy_mode != PHY_INTERFACE_MODE_SGMII &&
2021-02-12 1986 lp->phy_mode != PHY_INTERFACE_MODE_1000BASEX) {
2021-02-12 1987 dev_err(&pdev->dev, "xlnx,switch-x-sgmii only supported with SGMII or 1000BaseX\n");
2021-02-12 1988 ret = -EINVAL;
2021-03-11 1989 goto cleanup_clk;
2021-02-12 1990 }
2012-01-19 1991
2012-01-19 1992 /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */
2015-05-05 1993 np = of_parse_phandle(pdev->dev.of_node, "axistream-connected", 0);
2019-06-06 1994 if (np) {
2019-06-06 1995 struct resource dmares;
2019-06-06 1996
2015-05-05 1997 ret = of_address_to_resource(np, 0, &dmares);
2015-05-05 1998 if (ret) {
2019-06-06 1999 dev_err(&pdev->dev,
2019-06-06 2000 "unable to get DMA resource\n");
2019-03-22 2001 of_node_put(np);
2021-03-11 2002 goto cleanup_clk;
2015-05-05 2003 }
2019-06-06 2004 lp->dma_regs = devm_ioremap_resource(&pdev->dev,
2019-06-06 2005 &dmares);
2019-06-06 2006 lp->rx_irq = irq_of_parse_and_map(np, 1);
2019-06-06 2007 lp->tx_irq = irq_of_parse_and_map(np, 0);
2019-06-06 2008 of_node_put(np);
2020-03-24 2009 lp->eth_irq = platform_get_irq_optional(pdev, 0);
2019-06-06 2010 } else {
2019-06-06 2011 /* Check for these resources directly on the Ethernet node. */
2019-06-06 2012 struct resource *res = platform_get_resource(pdev,
2019-06-06 2013 IORESOURCE_MEM, 1);
2019-06-06 2014 lp->dma_regs = devm_ioremap_resource(&pdev->dev, res);
2019-06-06 2015 lp->rx_irq = platform_get_irq(pdev, 1);
2019-06-06 2016 lp->tx_irq = platform_get_irq(pdev, 0);
2020-03-24 2017 lp->eth_irq = platform_get_irq_optional(pdev, 2);
2019-06-06 2018 }
Kozlowski 2015-07-09 2019 if (IS_ERR(lp->dma_regs)) {
2015-05-05 2020 dev_err(&pdev->dev, "could not map DMA regs\n");
Kozlowski 2015-07-09 2021 ret = PTR_ERR(lp->dma_regs);
2021-03-11 2022 goto cleanup_clk;
2012-01-19 2023 }
2013-01-10 2024 if ((lp->rx_irq <= 0) || (lp->tx_irq <= 0)) {
2015-05-05 2025 dev_err(&pdev->dev, "could not determine irqs\n");
2012-01-19 2026 ret = -ENOMEM;
2021-03-11 2027 goto cleanup_clk;
2012-01-19 2028 }
2012-01-19 2029
2020-03-24 2030 /* Autodetect the need for 64-bit DMA pointers.
2020-03-24 2031 * When the IP is configured for a bus width bigger than 32 bits,
2020-03-24 2032 * writing the MSB registers is mandatory, even if they are all 0.
2020-03-24 2033 * We can detect this case by writing all 1's to one such register
2020-03-24 2034 * and see if that sticks: when the IP is configured for 32 bits
2020-03-24 2035 * only, those registers are RES0.
2020-03-24 2036 * Those MSB registers were introduced in IP v7.1, which we check first.
2020-03-24 2037 */
2020-03-24 2038 if ((axienet_ior(lp, XAE_ID_OFFSET) >> 24) >= 0x9) {
2020-03-24 2039 void __iomem *desc = lp->dma_regs + XAXIDMA_TX_CDESC_OFFSET + 4;
2020-03-24 2040
2020-03-24 2041 iowrite32(0x0, desc);
2020-03-24 2042 if (ioread32(desc) == 0) { /* sanity check */
2020-03-24 2043 iowrite32(0xffffffff, desc);
2020-03-24 2044 if (ioread32(desc) > 0) {
2020-03-24 2045 lp->features |= XAE_FEATURE_DMA_64BIT;
2020-03-24 2046 addr_width = 64;
2020-03-24 2047 dev_info(&pdev->dev,
2020-03-24 2048 "autodetected 64-bit DMA range\n");
2020-03-24 2049 }
2020-03-24 2050 iowrite32(0x0, desc);
2020-03-24 2051 }
2020-03-24 2052 }
2020-03-24 2053
2020-03-24 2054 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_width));
2020-03-24 2055 if (ret) {
2020-03-24 2056 dev_err(&pdev->dev, "No suitable DMA available\n");
2021-03-11 2057 goto cleanup_clk;
2020-03-24 2058 }
2020-03-24 2059
2019-06-06 2060 /* Check for Ethernet core IRQ (optional) */
2019-06-06 2061 if (lp->eth_irq <= 0)
2019-06-06 2062 dev_info(&pdev->dev, "Ethernet core IRQ not defined\n");
2019-06-06 2063
2012-01-19 2064 /* Retrieve the MAC address */
2021-04-06 2065 ret = of_get_mac_address(pdev->dev.of_node, mac_addr);
2021-04-06 2066 if (!ret) {
2021-04-06 2067 axienet_set_mac_address(ndev, mac_addr);
2021-04-06 2068 } else {
2019-06-06 @2069 dev_warn(&pdev->dev, "could not find MAC address property: %ld\n",
2019-06-06 2070 PTR_ERR(mac_addr));
^^^^^^^^^^^^^^^^^
2021-04-06 2071 axienet_set_mac_address(ndev, NULL);
2012-01-19 2072 }
2012-01-19 2073
Service, Intel Corporation
s://lists.01.org/hyperkitty/list/kbuild-all@xxxxxxxxxxxx">https://lists.01.org/hyperkitty/list/kbuild-all@xxxxxxxxxxxx
>.config.gz

_______________________________________________
kbuild mailing list -- kbuild@xxxxxxxxxxxx
To unsubscribe send an email to kbuild-leave@xxxxxxxxxxxx

Next message: Nobuhiro Iwamatsu: "[PATCH v3 1/2] dt-bindings: pwm: Add bindings for Toshiba Visconti PWM Controller"
Previous message: Alexandre Chartre: "Re: [PATCH 1/2] x86/traps: call cond_local_irq_disable before returning from exc_general_protection and math_error"
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]