Re: [PATCH v3 4/5] media: hantro: Use reset driver

[Benjamin Gaignard]

Le 03/03/2021 à 15:39, Philipp Zabel a écrit :
> On Mon, 2021-03-01 at 16:17 +0100, Benjamin Gaignard wrote:
> > Rather use a reset like feature inside the driver use the reset
> > controller API to get the same result.
> >
> > Signed-off-by: Benjamin Gaignard <benjamin.gaignard@xxxxxxxxxxxxx>
> > ---
> >   drivers/staging/media/hantro/Kconfig        |  1 +
> >   drivers/staging/media/hantro/imx8m_vpu_hw.c | 61 ++++-----------------
> >   2 files changed, 12 insertions(+), 50 deletions(-)
> >
> > diff --git a/drivers/staging/media/hantro/Kconfig b/drivers/staging/media/hantro/Kconfig
> > index 5b6cf9f62b1a..dd1d4dde2658 100644
> > --- a/drivers/staging/media/hantro/Kconfig
> > +++ b/drivers/staging/media/hantro/Kconfig
> > @@ -20,6 +20,7 @@ config VIDEO_HANTRO_IMX8M
> >   	bool "Hantro VPU i.MX8M support"
> >   	depends on VIDEO_HANTRO
> >   	depends on ARCH_MXC || COMPILE_TEST
> > +	select RESET_VPU_IMX8MQ
> >   	default y
> >   	help
> >   	  Enable support for i.MX8M SoCs.
> > diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c
> > index c222de075ef4..d5b4312b9391 100644
> > --- a/drivers/staging/media/hantro/imx8m_vpu_hw.c
> > +++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c
> > @@ -7,49 +7,12 @@
> >   
> >   #include <linux/clk.h>
> >   #include <linux/delay.h>
> > +#include <linux/reset.h>
> >   
> >   #include "hantro.h"
> >   #include "hantro_jpeg.h"
> >   #include "hantro_g1_regs.h"
> >   
> > -#define CTRL_SOFT_RESET		0x00
> > -#define RESET_G1		BIT(1)
> > -#define RESET_G2		BIT(0)
> > -
> > -#define CTRL_CLOCK_ENABLE	0x04
> > -#define CLOCK_G1		BIT(1)
> > -#define CLOCK_G2		BIT(0)
> > -
> > -#define CTRL_G1_DEC_FUSE	0x08
> > -#define CTRL_G1_PP_FUSE		0x0c
> > -#define CTRL_G2_DEC_FUSE	0x10
> > -
> > -static void imx8m_soft_reset(struct hantro_dev *vpu, u32 reset_bits)
> > -{
> > -	u32 val;
> > -
> > -	/* Assert */
> > -	val = readl(vpu->ctrl_base + CTRL_SOFT_RESET);
> > -	val &= ~reset_bits;
> > -	writel(val, vpu->ctrl_base + CTRL_SOFT_RESET);
> > -
> > -	udelay(2);
> > -
> > -	/* Release */
> > -	val = readl(vpu->ctrl_base + CTRL_SOFT_RESET);
> > -	val |= reset_bits;
> > -	writel(val, vpu->ctrl_base + CTRL_SOFT_RESET);
> > -}
> > -
> > -static void imx8m_clk_enable(struct hantro_dev *vpu, u32 clock_bits)
> > -{
> > -	u32 val;
> > -
> > -	val = readl(vpu->ctrl_base + CTRL_CLOCK_ENABLE);
> > -	val |= clock_bits;
> > -	writel(val, vpu->ctrl_base + CTRL_CLOCK_ENABLE);
> The way it is implemented in the reset driver, the clocks are now
> ungated between assert and deassert instead of afterwards. Is this on
> purpose?

No and that could be changed on next version.

Benjamin

> regards
> Philipp