Re: [PATCH v2 4/5] csky: Fixup asm/cmpxchg.h with correct ordering barrier

[Guo Ren]

Hi Peter,

On Thu, Jan 7, 2021 at 8:41 PM Peter Zijlstra <peterz@xxxxxxxxxxxxx> wrote:
>
> On Sun, Dec 20, 2020 at 03:39:22PM +0000, guoren@xxxxxxxxxx wrote:
>
>
> > +#define cmpxchg(ptr, o, n)                                   \
> > +({                                                           \
> > +     __typeof__(*(ptr)) __ret;                               \
> > +     __smp_release_fence();                                  \
> > +     __ret = cmpxchg_relaxed(ptr, o, n);                     \
> > +     __smp_acquire_fence();                                  \
> > +     __ret;                                                  \
> > +})
>
> So you failed to Cc me on patch #2 that introduces these barriers. I've
> dug it out, but I'm still terribly confused on all that.
>
> On first reading the above looks wrong.
>
> Could you also clarify the difference (if any) between your bar.brwarw
> and sync instruction?
>
> Specifically, about transitiviry, or whatever we seem to be calling that
> today.

bar.brwarw just like riscv fence.rwrw
bar means barrier
brw means before read and write would happen before the instruction.
arw means after read and write would happen after the instruction
So it also could be bar.brarw / bar.arw / bar.brw / bar.braw

sync means we need to wait until all instructions complete in the CPU
pipeline and then issue the next instructions.

-- 
Best Regards
 Guo Ren

ML: https://lore.kernel.org/linux-csky/