Re: [PATCH v8 3/4] phy: Add Sparx5 ethernet serdes PHY driver

[Steen Hegelund]

On 03.12.2020 22:52, Andrew Lunn wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> > +/* map from SD25G28 interface width to configuration value */
> > +static u8 sd25g28_get_iw_setting(const u8 interface_width)
> > +{
> > +     switch (interface_width) {
> > +     case 10: return 0;
> > +     case 16: return 1;
> > +     case 32: return 3;
> > +     case 40: return 4;
> > +     case 64: return 5;
> > +     default:
> > +             pr_err("%s: Illegal value %d for interface width\n",
> > +                    __func__, interface_width);
>
> Please make use of dev_err(phy->dev, so we know which PHY has
> configuration problems.

I will update that.

> > +static int sparx5_serdes_validate(struct phy *phy, enum phy_mode mode,
> > +                                     int submode,
> > +                                     union phy_configure_opts *opts)
> > +{
> > +     struct sparx5_serdes_macro *macro = phy_get_drvdata(phy);
> > +     struct sparx5_serdes_private *priv = macro->priv;
> > +     u32 value, analog_sd;
> > +
> > +     if (mode != PHY_MODE_ETHERNET)
> > +             return -EINVAL;
> > +
> > +     switch (submode) {
> > +     case PHY_INTERFACE_MODE_1000BASEX:
> > +     case PHY_INTERFACE_MODE_SGMII:
> > +     case PHY_INTERFACE_MODE_QSGMII:
> > +     case PHY_INTERFACE_MODE_10GBASER:
> > +             break;
> > +     default:
> > +             return -EINVAL;
> > +     }
> > +     if (macro->serdestype == SPX5_SDT_6G) {
> > +             value = sdx5_rd(priv, SD6G_LANE_LANE_DF(macro->stpidx));
> > +             analog_sd = SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_GET(value);
> > +     } else if (macro->serdestype == SPX5_SDT_10G) {
> > +             value = sdx5_rd(priv, SD10G_LANE_LANE_DF(macro->stpidx));
> > +             analog_sd = SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_GET(value);
> > +     } else {
> > +             value = sdx5_rd(priv, SD25G_LANE_LANE_DE(macro->stpidx));
> > +             analog_sd = SD25G_LANE_LANE_DE_LN_PMA_RXEI_GET(value);
> > +     }
> > +     /* Link up is when analog_sd == 0 */
> > +     return analog_sd;
> > +}
>
> What i have not yet seen is how this code plugs together with
> phylink_pcs_ops?
>
> Can this hardware also be used for SATA, USB? As far as i understand,
> the Marvell Comphy is multi-purpose, it is used for networking, USB,
> and SATA, etc. Making it a generic PHY then makes sense, because
> different subsystems need to use it.
>
> But it looks like this is for networking only? So i'm wondering if it
> belongs in driver/net/pcs and it should be accessed using
> phylink_pcs_ops?
>
>        Andrew

This is a PHY that communicates on a SerDes link to an ethernet PHY or a
SFP. So I took the lead from earlier work: the Microsemi Ocelot SerDes driver,
and added the Sparx5 SerDes PHY driver here since it is very similar in intent.
It is not an ethernet PHY as such.

BR
Steen

---------------------------------------
Steen Hegelund
steen.hegelund@xxxxxxxxxxxxx