Re: [PATCH 0/3] x86: Add initial support to discover Intel hybrid CPUs

[Ricardo Neri]

On Sat, Oct 03, 2020 at 12:46:29PM +0200, Thomas Gleixner wrote:
> On Fri, Oct 02 2020 at 19:17, Tony Luck wrote:
> 
> > On Sat, Oct 03, 2020 at 03:39:29AM +0200, Thomas Gleixner wrote:
> >> On Fri, Oct 02 2020 at 13:19, Ricardo Neri wrote:
> >> > Add support to discover and enumerate CPUs in Intel hybrid parts. A hybrid
> >> > part has CPUs with more than one type of micro-architecture. Thus, certain
> >> > features may only be present in a specific CPU type.
> >> >
> >> > It is useful to know the type of CPUs present in a system. For instance,
> >> > perf may need to handle CPUs differently depending on the type of micro-
> >> > architecture. Decoding machine check error logs may need the additional
> >> > micro-architecture type information, so include that in the log.
> >> 
> >> 'It is useful' as justification just makes me barf.
> >
> > This isn't "hetero" ... all of the cores are architecturally the same.
> 
> The above clearly says:
> 
> >> > A hybrid part has CPUs with more than one type of micro-architecture.
> 
> Can you folks talk to each other and chose non-ambigous wording in
> changelogs and cover letters?
> 
> > If CPUID says that some feature is supported, then it will be supported
> > on all of the cores.
> 
> That's a different story.

Thank you for the quick reply, Thomas.

I am sorry if my cover letter was not sufficiently clear. I see now that
I should have done a more detailed discussion of the terminology.

Yes, all features and instructions as enumerated in CPUID will be
supported in all CPUs. Thus, the kernel will not have to check if a
feature is supported before running. The hetero/hybrid part means to
reflect that more than one types of CPUs will be present in the package,
and the main difference is power and performance. The same kernel and user code
will run on all CPUs without any other further check.

> 
> > There might be some model specific performance counter events that only
> > apply to some cores. Or a machine check error code that is logged in the
> > model specific MSCOD field of IA32_MCi_STATUS. But any and all code can run
> > on any core.
> 
> Ok. The perf side should be doable, IIRC we already have something like
> that, but Peter should know better.
> 
> > Sure there will be some different power/performance tradeoffs on some
> > cores. But we already have that with some cores able to achieve higher
> > turbo frequencies than others.
> 
> Right, that's not a problem.

We are also working this front.

Thanks and BR,
Ricardo