[PATCH v3 0/6] clk: axi-clk-gen: misc updates to the driver

From: Alexandru Ardelean
Date: Thu Sep 24 2020 - 02:50:43 EST


These patches synchronize the driver with the current state in the
Analog Devices Linux tree:
https://github.com/analogdevicesinc/linux/

They have been in the tree for about 2-3, so they did receive some
testing.

Highlights are:
* Add support for fractional dividers (Lars-Peter Clausen)
* Enable support for ZynqMP (UltraScale) (Dragos Bogdan)
* Support frequency limits for ZynqMP (Mathias Tausen)
- And continued by Mircea Caprioru, to read them from the IP cores

Changelog v2 -> v3:
* for patch 'include: fpga: adi-axi-common.h: add definitions for supported FPGAs'
- fix whitespace found by checkpatch
- add 'Acked-by: Moritz Fischer <mdf@xxxxxxxxxx>'

Changelog v1 -> v2:
- in patch 'include: fpga: adi-axi-common.h: add definitions for supported FPGAs'
* converted enums to #define
* added Intel FPGA definitions
* added Device-Package definitions
* added INTEL / XILINX in the define names
definitions according to:
https://github.com/analogdevicesinc/hdl/blob/4e438261aa319b1dda4c593c155218a93b1d869b/library/scripts/adi_intel_device_info_enc.tcl
https://github.com/analogdevicesinc/hdl/blob/4e438261aa319b1dda4c593c155218a93b1d869b/library/scripts/adi_xilinx_device_info_enc.tcl

Dragos Bogdan (1):
clk: axi-clkgen: add support for ZynqMP (UltraScale)

Lars-Peter Clausen (2):
clk: axi-clkgen: Add support for fractional dividers
clk: axi-clkgen: Set power bits for fractional mode

Mathias Tausen (1):
clk: axi-clkgen: Respect ZYNQMP PFD/VCO frequency limits

Mircea Caprioru (2):
include: fpga: adi-axi-common.h: add definitions for supported FPGAs
clk: axi-clkgen: Add support for FPGA info

drivers/clk/Kconfig | 2 +-
drivers/clk/clk-axi-clkgen.c | 253 ++++++++++++++++++++++------
include/linux/fpga/adi-axi-common.h | 103 +++++++++++
3 files changed, 302 insertions(+), 56 deletions(-)

--
2.25.1