Re: [PATCH v1 2/2] perf/core: Fake regs for leaked kernel samples

[Jin, Yao]

Hi Peter,

On 8/6/2020 7:00 PM, peterz@xxxxxxxxxxxxx wrote:
> On Thu, Aug 06, 2020 at 11:18:27AM +0200, peterz@xxxxxxxxxxxxx wrote:
>
> > Suppose we have nested virt:
> >
> > 	L0-hv
> > 	|
> > 	G0/L1-hv
> > 	   |
> > 	   G1
> >
> > And we're running in G0, then:
> >
> >   - 'exclude_hv' would exclude L0 events
> >   - 'exclude_host' would ... exclude L1-hv events?
> >   - 'exclude_guest' would ... exclude G1 events?
>
> So in arch/x86/events/intel/core.c we have:
>
> static inline void intel_set_masks(struct perf_event *event, int idx)
> {
> 	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
>
> 	if (event->attr.exclude_host)
> 		__set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
> 	if (event->attr.exclude_guest)
> 		__set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
> 	if (event_is_checkpointed(event))
> 		__set_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
> }

exclude_host is now set by guest (pmc_reprogram_counter, arch/x86/kvm/pmu.c). When enabling the 
event, we can check exclude_host to know if it's a guest.

Otherwise we may need more flags in event->attr to indicate the status.

> which is, afaict, just plain wrong. Should that not be something like:
>
> 	if (!event->attr.exclude_host)
> 		__set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
> 	if (!event->attr.exclude_guest)
> 		__set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);

How can we know it's guest or host even if exclude_host is set in guest?

Thanks
Jin Yao

> Also, ARM64 seems to also implement this stuff, Mark, do you have any
> insight on how all this is 'supposed' to work?